One of the interesting charts to emerge from today’s launch of IC Compiler II by Synopsys is the difference between the US, Japan and Europe on the speed up the tool is showing.
European designs are seeing a 6 or 7x speed up in design planning rather than 10 or 20x from designs in other regions. This is down to more focus on IP rather than the influence of mixed signal or analog designs, says Saleem Haider, senior director of marketing for physical design at Synopsys.
"I think part of the issue with the European instances is these designs are very IP dominated than, for example the Japanese designs, so there is less opportunity for big speedups," he said. "Even so, a 6x or 7x speed up , customers are snatching the product out of our hands. Previously if the design planning flow took a day, and that’s fast, now you can do several exploration turns in a day. But also bear in mind that some of this IP itself (CPUS and GPUs) have a fairly complex implementation process and that can benefit a lot from more automation and more speed up."
The speed up allows more of the design space to be explored. "A design with 3m cells takes several days for planning so if we can speed that up by 5x that’s results in a day rather than a week and that to customers is game changing. It’s not that they saved four days, its what they can do with it – instead of having a 1m cell partition having a 3m partition and get better results, or do it 5 times and go for lower power," he said.
The heart of the new tool is a database and data format that is more suited to multi-threaded, multi-user operation, and this has speeded up the existing tools. Some elements such as timing and optimization have been re-designed, while the placer and routing engines have not been changed.
"We’ve been working on this for a number of years and the initial feedback from customers is very positive," said Haider. "We basically had a two part strategy to keep IC compiler going strong but we also started a new initiative to start from scratch to achieve a 10x speed up. One P&R system is complex enough to build and maintain and we are talking about two."
"We redid the timing engine and completely redid the optimization engine and the approach to hierarchy is completely different," he said. "The clock construction is also designed from the ground up. But we don’t have to re-do anything, the routing engine and placer are the best in the world.""
The acquisition of Magma Design Systems in February 2012 was a key part of the development. "We got technology and a lot of technologists," he said. "The Volcano concept in Magma was very popular with the ability to take a snapshot of the design and save it, and we are using that instead of Milky Way."
The Magma deal also brought new customers to test the tool on. "Having the collaborative access to customers is a big part of it as it’s just not possible to build a system like this in isolation," he said. "You need to have a good range of designs so that the new technology can be tested out. It’s been many years in the works."
Part of this change is a new incremental timer that’s multi-threaded-friendly. The clock tree is completely rebuilt to support more global optimization, he says. The traditional approach is to optimize different paths independently and the optimization is through the delay and one branch relative to the other. "We get pretty good results with that flow, and this powers today’s chips, but it’s expensive and the paths can be very, very large," he said. "So the new approach is more global with a network solver that looks at the tree overall and computes the delay."
He expects to see 10-15 design starts this year with the tool, including the existing early access customers. "We have seven or so active designs in different stages of tapeout using the partial systems," he said. "We have some customers who have done a partition with the early software and they are looking to proliferate to other designs so I think in 2015 we will blow past the 20-30 range."