It may come as a surprise that over 10 billion RISC-V processor cores have shipped. After all, it took ARM 17 years to reach that milestone in 2008, and RISC-V could be considered to be in its infancy with a consensus that the eco-system still needs to evolve, particularly around security.
These two factors result from the open standard approach to an inherently custom technology. The instruction set can be easily extended to accelerate key instructions, reducing die area and boosting performance. As a result many chip makers are using the technology embedded in devices with custom extensions without the need for external tools.
The open standard is key, Calista Redmond, CEO of RISC-V International told eeNews Europe at the recent Embedded World exhibition.
“Linux did this for software and we are doing this for hardware,” she said. “We estimate there are 10bn cores on the market already,” she said.
This is mainly down to custom cores embedded into other devices to handle specific functions. “We have one customer facing processor in a chip but four or five other processors in our chips,” said Daniel Cooley, Chief Technology Officer and Senior Vice President, Technology and Product Development at Silicon Labs.
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The show saw the launch of RISC-V cores developed in Europe, from the embedded designs from Imagination Technologies to a development kit for the Internet of Things (IoT) from the Open Hardware Group with key support from European developers such as Imperas and Embecosm.
“The momentum behind RISC-V is huge,” Chris Porthouse, Chief Product Officer at Imagination Technologies told eeNews Europe at the show as its launched a family of real time RISC-V CPU cores for embedded controllers. “There is a change coming in the industry and I think its unstoppable,” he said.
He points to the backing of controversial private equity fund Canyon Bridge as key to supporting recruitment of staff in Cambridge, Manchester and Bristol for product development. “Canyon Bridge put a lot of money into the business and that has allowed us to move faster,” he said. “This is a ten year investment for us and we are investing at the right level to intersect the market.”
It has previously worked with RISC-V core suppliers Andes in Taiwan and SiFive in the US, as well as the SWERV core from Western Digital to give it the experience to launch its own cores and associated tools.
GigaDevice Semiconductor is one startup that has adopted RISC-V to drive its microcontroller business, first in China and now in Europe. After winning an award at Embedded World in 2020 for its first RISC-V device the GD32VF103 for Cost conscious or dedicated applications, supported by a tool chain from IAR.
“Europe is a very important market for MCU it’s a small team of 10 but we are growing,” said Ren Sun, MCU marketing manager for EMEA. The development tools are vital for both the ARM and RISC-V devices.
“For generic MCUs you have generic ecosystem support and its amazing how fast customers can migrate to our devices,” he said. “We chose a very customer friendly approach to be package and pin compatible with existing devices and we are doing new products.”
He points to the GD32W515 ARM wireless MCU with WiFi using the Cortex-M33 with TrustZone security. “We brought our experience from the generic MCU market and for higher performance we will go to M7 and security is an important feature,”
The company is planning its next 32bit RISC-V chip. “We have another RISC-V product coming, it could be IoT with connectivity – its definitely something we are continuously developing,” he said.
The technology is also a key part of providing sovereign processor technology in Europe. Codasip, headquartered in Munich, develops cores and tools for custom variants.
“Being European is a huge part of the strategy,” said Rupert Baines, chief marketing officer of Codasip told eeNews Europe. “All of our R&D is in Europe so we can sell to the US and sell to China. There’s a lot of European companies that are moving into RISC-V. Europe was slow into RISC-V and the adoption is happening in the same way that is did in the US and Asia.”
He points to NXP Semiconductor, which hasn’t officially launched any RISC-V devices so far but is part of the OpenHardware group along with European technology group Thales, which this week sponsored its second RISC-V student design challenge in Strasbourg.
“Open hardware is a pillar of Thales’s innovation strategy, alongside artificial intelligence, quantum technologies, connectivity and cybersecurity,” said Bernhard Quendt, Chief Technology Officer of Thales. “We are determined to support any initiative that brings greater autonomy, sovereignty and flexibility to the development of customer solutions, because we believe those attributes are key differentiators in the defence and security markets we serve.”
“We can see the value of being part of the OpenHardware group,” said Baines at Codasip. “We have a portfolio of standard RISC-V products and about half of our customers take these as standard and for the other half we ship an architecture license and the tools to modify the cores for their unique applications,“ he said.
At the show the company support for quantum-resistant secure tools from Veridify Security on its cores for a secure-boot function. Veridify’s secure algorithm validates firmware as it loads onto the Codasip processor to reassure RISC-V developers that embedded systems are secure.
Veridify’s secure boot functionality is based on an algorithm that runs faster than traditional encryption methods; only requiring a small code space and ultra-low power making it well-suited to Codasip’s family of low-power embedded processors.
“We are pleased to have been chosen by Codasip to provide future-proof secure boot functionality on its low-power RISC-V processors,” said Louis Parks, chairman and CEO of Veridify. “Codasip customers can now trust that their firmware is authentic during the boot process and have confidence that their Codasip processor is safe and secure for the life of their device.”
“One company in security software whose offering is partly based on standards driven by ARM said they were expanding into RISC-V, because their customers wanted easier migration from ARM to RISC-V,” said Roddy Urquhart, senior marketing director at Codasip “In contrast though, another security software company said that for them they were not yet ready to support RISC-V based on the limited number production RISC-V devices in the field. But given the interest in RISC-V that would change in time. The industry is definitely at a tipping point.”
Another major RISC-V supplier, SiFive, enhanced its X280 processor IP for the growing demand for AI inference and image processing.
The company has just opened its UK design centre in Cambridge, like Imagination tapping into the pool of skills in the area.
The design is scalable to a 16-core cache-coherent complex with security from WorldGuard and a new interface allowing for integration between the X280 vector unit and customer-designed external AI accelerators or other coprocessors, called VCIX (Vector Coprocessor Interface eXtension).
The X280 is the most widely adopted implementation of the RISC-V Vector extension with over ten design wins in the last six months.
“The market feedback about our X280 has been nothing short of incredible. The product maps extremely well to the needs of the modern workload and vector processing and was introduced at the exact right moment to accelerate RISC-V’s already considerable momentum,” said Chris Jones, VP Product at SiFive and formely at Codasip and Tensilica. “The X280 enhancements are a direct result of listening and collaborating with customers and are already designed into multiple sockets around the world. Additionally, the software ecosystem around the RISC-V vector extension is growing exponentially which ensures broad support for customers and is driving the inevitable, wide industry adoption of RISC-V.”
All of this highlights the momentum behind the open standard and the maturing of the eco-system. With established RISC-V compilers, linkers and debuggers from European suppliers Segger, IAR and Lauterbach, there is established competition for Ashling, which is working with Intel and MIPS on tools for RISC-V cores.
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