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European supercomputer project receives RISC-V test chips

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By Nick Flaherty


The EPI project has 28 partners from 10 European countries, with the goal of making EU achieve independence in HPC chip technologies and HPC infrastructure. 43 of the EPAC1.0 RISC-V test chips were delivered to EPI from GlobalFoundries and initial tests of their operation were successful.

The European Processor Accelerator (EPAC) combines several accelerator technologies specialized for different application areas. Built in a 22nm process, the 1GHz chips have an area of 26.97mm2 with 14 million placeable instances, equivalent to 93m gates, including 991 memory instances

The test chip contains four vector processing micro-tiles (VPU) composed of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Centre and the University of Zagreb.

Each tile also contains a Home Node and L2 cache, designed respectively by Chalmers and FORTH, to provide a coherent view of the memory subsystem.

The chip also includes two additional accelerators: the Stencil and Tensor accelerator (STX) designed by Fraunhofer IIS, ITWM and ETH Zürich, and the variable precision processor (VRP) by CEA LIST. All accelerators on the chip are connected with a very high-speed network on chip and SERDES technology from EXTOLL.

The chips were fabricated in GF’s 22FDX low-power technology and are packaged in FCBGA with 22×22 balls

Initial bring-up was successful and EPAC executed its first bare metal program sending the traditional “Hello World!” greetings in different languages to EPI consortia and the world!

EPI says it will continue to develop, optimize and validate different IP blocks and demonstrate features and performance of those thus creating an EU HPC IP ecosystem and make it available to the processor and accelerator industry and academia for the next generation HPC systems.

www.european-processor-initiative.eu/

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