European system-in-package research programme yields results
Infineon reports that the largest research project in Europe aimed at developing highly integrated system-in-package solutions has been successfully completed. ESiP (Efficient Silicon Multi-Chip System-in-Package Integration) project partners have worked out future system-in-package solutions that will be more compact and reliable. They have also developed methods for simplifying analyses and tests. Under management by Infineon Technologies, 40 research partners – microelectronics companies and research institutions – from a total of nine European countries worked together.
System-in-Package (SiP) means different types of chips made using different production techniques and structure widths are embedded side by side or stacked above one another in one chip package and work efficiently together.
Technologies for combining chips in SiP packages and manufacturing them were developed, along with procedures for measuring reliability, plus methods and equipment for failure analysis and testing. Basic technologies were developed that enable the integration of various types of chips in the smallest volume of an SiP package, for example, customer-specific processors with the latest CMOS technologies, light-emitting diodes and DC-DC converters, MEMS and sensor components and passive components such as miniaturised capacitors and inductors.
With ESiP, production processes were developed for SiP solutions with two or more very different chips in one package. New materials for building SiP solutions were also investigated. The research partners have proved the feasibility and reliability of the new production processes with more than 20 different test vehicles. In the course of the research work it was confirmed that the test procedures commonly used today are no longer sufficient for future SiP solutions: new test flows, probe stations and probe adapters were developed for 3D SiP.
“The successful ESiP research enhances Europe’s position in the development and manufacture of miniaturized microelectronics systems,” says Dr. Klaus Pressel, ESiP project head and responsible for international cooperation on assembly and packaging solutions at Infineon Technologies. “With the ESiP findings we will be able to further miniaturise and improve microelectronic systems. We have developed new manufacturing processes and materials for SiP solutions along with methods for testing them, running a failure analysis on them and evaluating their reliability.”
The overall ESiP budget totaled around €35million, with half of this financed by the 40 project partners. Of the other half two thirds were provided by national funding organisations in Austria, Belgium, Finland, France, Germany, Great Britain, Italy, the Netherlands and Norway, and one third by the European Union through its ENIAC Joint Undertaking. In Germany, the BMBF sponsored the ESiP project as part of the Information and Communications Technology 2020 program (IKT 2020) to the tune of around €3.1million, along with funding from the Free State of Saxony.
EsiP programme; www.eniac.eu/web/downloads/projectprofiles/call2_eniac_esip.PDF
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