Europe’s RISC-V processor developer up for sale
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The board of directors at Codasip in Germany has put the RISC-V processor developer up for sale.
The company, under CEO Ron Black, is looking to sell the company in the next three months. It has developed tools to produce processor cores using the open RISC-V instruction set and has funding of up with €380m with various equity and grants that includes follow on project funding. There are currently 250 staff, 57% in hardware and 30% in software.
RISC-V development has struggled in recent years with more competition in the market. Synopsys launched a full range of RISC-V core IP last year, while the Quintauris consortium of major chip makers is also developing RISC-V processors. US RISC-V core developer SiFive restructuring in 2023.
The company has struggled over recent years, with founder Karel Masarik moving to run the Codasip Labs subsidiary in 2022.
- CHERI SDK donated to open source
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Black says there are grants and equity of €119 million, most of which is still to be received by the company. Follow-on funding totals a further €210 million for a total of €329 million, and the company is part of new consortiums and projects that can bring in an additional €51 million or more in future financing.
Codasip has received early interest in being acquired, which has triggered the board to initiate the accelerated sale or breaking up, as it has four key product areas with separable R&D teams.
Studio is an electronic design automation (EDA) tool for developing and customizing the RISC-V processors.
There is a portfolio of standard application and embedded RISC-V processors developed with Studio but also available in industry standard RTL and all available in Automotive grade (Safe and Secure as defined by ISO26262 and ISO/SAE 21434). Each of these processors can be customized with Studio. This portfolio is largely complete and therefore associated with a smaller portion of the EU financing.
There is also a portfolio of application and embedded RISC-V processors and complementary software based on the memory-safe CHERI (Capability Hardware Enhanced RISC Instructions) standard.
Finally a portfolio of high-performance application processors are being developed and benefit from the bulk of the EU financing as part of the DARE project.
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