EUV lithography: 32nm pitch on a single exposure

EUV lithography: 32nm pitch on a single exposure

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By eeNews Europe

Imec’s approach to enable EUV single patterning at these dimensions is based on the co-optimization of various lithography enablers, including materials, metrology, design rules, post processing and a fundamental understanding of critical EUV processes. With its results, IMEC expects to significantly impact the technology roadmap and wafer cost of near-term technology nodes for logic and memory.

With the industry making significant improvements in EUV infrastructure readiness, first insertion of EUV lithography in high-volume manufacturing is expected in the critical back-end-of-line metal and via layers of the foundry N7 Logic technology node, with metal pitches in the range of 36–40nm.

IMEC’s research focuses on the next node (32nm pitch and below), where various patterning approaches are being considered. These approaches vary considerably in terms of complexity, wafer cost, and time to yield, and include variations of EUV multi-patterning, hybrid EUV and immersion multi-patterning, and EUV single expose.

The research centre advances include initial electrical results for EUV single exposure focusing on two primary use cases: logic N5 32nm pitch metal-2 layer and 36nm pitch contact hole arrays.

Working with its many materials partners, IMEC assessed different resist materials strategies, including chemically amplified resists, metal-containing resists and sensitizer-based resists. Particular attention was paid to the resist roughness, and to nano-failures such as nanobridges, broken lines or missing contacts that are induced by the stochastic EUV patterning regime. These stochastic failures are currently limiting the minimum dimensions for single expose EUV. This work allowed IMEC to identify the primary dependencies influencing failures and deploy various metrology techniques and hybrid strategies to ensure an accurate picture of the reality of stochastics.

EUV single patterning of (left) the N5 32nm metal-2 layer, (middle) 32nm
pitch dense lines, and (right) 40nm hexagonal contact holes and pillars.

As resist materials advances alone will likely be insufficient to meet the requirements, researchers at IMEC have also focused on co-optimizing the photomask, film stack, EUV exposures and etch towards an integrated patterning flow to achieve full patterning of the structures.

This was done using computational lithography techniques such as optical proximity correction and source mask optimization, complemented by design-technology co-optimization to reduce standard library cell areas. Finally, etch-based post-processing techniques aimed at smoothing the images after the lithography steps yields encouraging results for dense features. Co-optimization of these multiple knobs is key to achieving optimized patterning and edge placement error control.
Imec –

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