EV Group, ASM partner for 3D-IC, chiplet bonding

EV Group, ASM partner for 3D-IC, chiplet bonding

Business news |
By Peter Clarke

Die-to-wafer hybrid bonding is a key process for enabling 3D stacked chips and chiplet style packaging, where chips from different process nodes and IC manufacturing processes are combined in advanced packaging. The technique is expected to be used in 5G circuits, high-performance computing and artificial intelligence (AI).

Hybrid bonding involves both wafer-to-wafer and die-to-wafer integration which have historically been separate processes performed at different stages of component production. The challenge faced by EV Group and ASM is to merge ultra-high-precision bonding, wafer fabrication, die preparation and handling in a Class 1 cleanroom environment and hybrid and fusion bonding into a seamless approach.

EV Group brings die preparation and front-end cleanliness experience to the joint development. ASM provides precision die-bonding capabilities. The ultimate goal of die-to-wafer hybrid bonding is to reduce both the time to market and non-recurring engineering development costs by directly fusing the copper interconnects and dielectric of pre-developed chiplets. ASM claims it can provide 200nm accuracy for the placement of chiplet die.

The joint development will take place at R&D facilities in Europe and Asia.

Markus Wimplinger, technology development director at EVG, said: “Heterogeneous integration provides a critical pathway forward for the semiconductor industry to realize continued innovation. EVG has invested significant resources to support this transition, by developing advanced process solutions, including industry-leading wafer-to-wafer and die-to-wafer hybrid bonding platforms, as well as creating our Heterogeneous Integration Competence Center, which serves as an open access innovation incubator for customers and partners to accelerate the development of new and differentiating heterogeneous integration products and solutions.”

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