Evaluate ADI’s latest converters with the Virtual Eval tool, on your PC
Having chosen a device, opening the Eval tool initially shows (above, and repeated below for size/clarity) a block diagram of the selected part, showing the layout of its major sections. Each block in the diagram that is user configurable, is ientified by highlighting, and has a corresponding entry on the settings menu.
The user can enter their own chosen values in each of the field, and can then set the operating parameters for the device (clock speed, input signal frequency, etc. Each time a setting is changed, the parameter is changes to being shown in bold face to indicate that the simulation with that parameter has not yet been executed. The user can then run the simulation; a greyed-out ‘run’ box indicates that the current set of input conditions has been simulated, and results are available.
After a run a number of tabs are presented to show each of the key metrics of performance, such as waveforms or frequency response plots. Graphs are ‘live’ – a cursor positioned on a graph will read out the instantaneous value. There is also a zoom/pan function. A results history is maintained over the session, and results can be downloaded.
14bit, 500 MHz, quad ADC
Newly-posted on ADI’s website is the AD9694, a quad, 14-bit, 500 Msample/sec analogue-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analogue signals of up to 1.4 GHz. The AD9694 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
ADI intends the 9694 for use in general communications; in diversity multiband, multimode digital receivers for 3G/4G, W-CDMA, GSM, LTE, LTE-A; in general-purpose software radios and ultrawideband satellite receivers; in instrumentation, and in radars and signal intelligence (SIGINT). More on details from the product page, below.
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When the virtual evaluation is invoked for this part, the fist screen capture shown, appears. The key internally configurable attribute of the device is to enable or disable the digital down-converter blocks; there is a field to do so. You can then choose to feed the converter a single tone, or dual tone, and you can set the frequency and amplitude of each. Other operating conditions for the simulation are jitter, and clock speed.
The key metric in this case (AD9694) is the output amplitude/frequency (FFT) plot and this is shown for the “starting point” conditions that the simulator is loaded with. The fundamental and main harmonic components are picked out and labelled. Top left is the +/- button to zoom; panning is by a slider a the bottom of the graph. Key parameters are tabulated alongside the graph.
In the last screen capture, the output is shown for a two-tone input. Significant components in the output are picked out, and their sources identified (for example, in the screen capture, ‘3F1+3F2’).
AD9694, continued…
[from the product page, link below] The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
The analogue inputs and clock signals are differential inputs. Each pair of ADC data outputs is internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters.
In addition to the DDC blocks, the AD9694 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an over-range condition at the ADC input.
Users can configure each pair of intermediate frequency (IF) receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins.
The AD9694 has flexible power-down options that can be programmed using the 1.8 V capable, 3-wire SPI. An evaulation board is available;
Key features are;
Low power consumption per channel.
JESD204B lane rate support up to 15 Gbps.
Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz.
Buffered inputs ease filter design and implementation.
Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.
Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.
Programmable fast overrange detection.
On-chip temperature diode for system thermal management.
Analog Devices; www.analog.com/ad9604 and www.analog.com
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