Examining high current and high power density demands on POL converters

Examining high current and high power density demands on POL converters

Technology News |
By eeNews Europe

The complexity and performance of the latest FPGAs, processors, ASICs and associated memories for server, telecom, datacom, networking, and industrial equipment continue to increase the power demands in these applications. Real estate remains at a premium driving the requirements for higher power density point-of-load (POL) solutions due to the conflicting objectives of increasing output capacity while maintaining or even reducing the solution board footprint.
From the power design viewpoint, this introduces three specific challenges: thermal management, compactness of the power solution footprints and improved transient response.  Undertaking all three challenges simultaneously can take significant power expertise and design resources; hence, many system designers are turning to modules as a way to quickly and reliably achieve the high current and high density point-of-load (POL) design they need. 
Packaging Matters

One of the keys to achieving high current and high density power converter design is thermal management. Managing thermal issues is one of the greatest challenges in high power (greater than 100W) applications.  Footprint and ultimately power rating, especially at high ambient temperature, are dictated by the module’s electrical and mechanical design.  Using thermally enhanced packages that can efficiently move heat out of the package enables modules to deliver better thermal performance.
A power module is typically built upon a package substrate on which the semiconductor die and other electronic components are mounted and inter-connected. It is therefore imperative for this package substrate to provide good thermal conductivity.
A variety of different types of package substrates are utilized in power modules. A dual layered printed circuit board in a land grid array (LGA) power module provides a substrate with good routing capability and straightforward electrical interconnections. The thermal conductivity, however, is undesirably low and will penalize the module thermal performance. An alternative approach, using a metal lead fame on a quad flat no leads (QFN) package, provides very good thermal conductivity but lacks the ease of routing capability. While the QFN can be modified to improve the routing, this technique usually results in higher package costs.
The best combination of thermal conductivity and routing capability is a single-layer conductive package substrate in a High Density lead-frame Array (HDA). This substrate comprises a peripheral and an interior portion. The peripheral portion includes contact pads used for surface mount on a motherboard while the interior portion includes floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to internal components. The peripheral and interior contact pads of the HDA lead-frame in combination with bond or jumper wires allow the HDA power module to provide excellent routing capabilities, similar to that of a dual-layered PCB, as well as excellent thermal conductivity to dissipate heat because of the single conductive layer of material.
Thermal images of the ISL8272M encapsulated digital power module running a continuous 50A load are shown in Figure 1. Mounted on a 2oz. 6-layer FR4 4.7 inch by 4.8 inch board, the ISL8272M performs outstandingly in a thermal test, providing a non-derated 50A capacity even under the worst case condition of a 14V input voltage to 5V output voltage conversion ratio. The module achieves an ultra-high power density of >1300W/in3.

Figure 1. Thermal images of the ISL8272M.  (a) VIN=12V, VOUT=1V, IOUT=50A, FSW=300kHz, TA=25°C, 0LFM (no air flow). (b) VIN=14V, VOUT=5V, IOUT=50A, FSW=533kHz, TA=25°C, 0LFM (no air flow).

Compact Power Footprint

Many applications are space constrained. System designers are often forced to select between using an undersized inductor, which can lead to poor efficiency, or the addition of a bulky heat sink to try and improve efficiency. Generally speaking, inductors must be designed sufficiently large to achieve low DC Resistance (DCR) copper loss and core loss, while maintaining a reasonable operating temperature.
A 3D stackable inductor structure addresses both the space and efficiency constraints.  In this structure, the inductor can be designed almost as large as the entire power module footprint and installed over the other components. This technique significantly reduces the substrate area compared to a side-by-side mounting method, hence a much smaller DCR loss and core loss can be achieved within a reduced footprint.

Figure 2 illustrates the cross-sectional view of two types of power module structures in concept. In Figure 2(a), a multi-layer PCB is utilized as the package substrate to provide flexibility of electrical interconnections and routings; the inductor is mounted side-by-side from the other components (controller, FETs, and passives). In this structure and as noted earlier, the heat transfer efficiency can be poor due to the low thermal conductivity of the multi-layer substrate. With limited footprint space, it is often forced to use an undersized inductor. Since the inductor height dominates the module dimension in the Z-axis, any saving from the inductor’s X-Y dimensions could result in an increase of the inductor height and thus a waste of the module’s form factor. In addition, the concentrated inductor structure also prevents efficient top- and bottom-side cooling.
Figure 2(b) shows the HDA power module structure with 3D inductor integration. The single-layer copper lead-frame with both the peripheral and interior portions (not shown) offers similar routing capabilities to a dual-layer PCB and much higher thermal conductivity. By installing the inductor on top of other components, the space along the Z-axis is efficiently utilized. The module footprint area is reduced while simultaneously minimizing the inductor DCR and core losses. In addition, heat concentration at the inductor is easily avoided due to the reduced inductor loss and effective large heat dissipation area.


Figure 2. Cross-sectional view of two types of power module structures
In Figure 3, we have a real-life example of the power loss breakdown of an actual module leveraging the 3D inductor design in an HDA package compared with the traditional dual-phase 50A design incorporating two side-by-side mounted inductors. The total inductor loss can be reduced from 3W to 1.3W for a 12V input to 1V output at 50A load current application. Hence, the full load efficiency reaches 88.3%, a much better figure than the 85.7% efficiency of the traditional design.

Figure 3. Power loss comparison between ISL8272M and the typical design with two separate inductors side-by-side.  Operating conditions: VIN=12V, VOUT=1V, IOUT=50A, FSW=533kHz, TA=25°C.
Improving Transient Response

In addition to electromechanical design considerations addressing the thermal issues and POL footprint, transient response performance cannot be neglected.  Digital power management provides some of the best-in-class techniques to improve a POL control loop transient response.
Digital power management equips systems with real-time intelligence and flexibility. It allows automatic compensation for changes in load and temperature, dynamic voltage scaling, frequency shifting, phase dropping and on-the-fly configurations. It also provides full telemetry and monitoring of the system operating parameters.
Digital control makes it possible to build far more flexible control loops by incorporating n x FSW (switching frequency) oversampling, multi-rate sampling, and various types of digital filters for notching and phase shaping, Fourier transform, and so on. Such features associated with complex digital signal processing are often not feasible with traditional analog control techniques.

In Figure 4, the control block diagrams of a typical Type III analog compensation and a fast response digital compensation are illustrated for comparison.

Figure 4. Analog vs. digital compensations for voltage mode controlled buck converter

In the Figure 4(b) control loop example, the analog-to-digital converter (ADC) is over sampling at a frequency of n x FSW, where n >> 1. Therefore, the phase lag or group delay introduced by the analog-to-digital conversion is negligible for the loop stability. Because of the over sampling, it is feasible to design the core compensator Gc(z-1) to have a similar frequency response to the two-zero two-pole compensator in Figure 4(a) in terms of loop gain and phase. Most importantly, the filter employed to attenuate the high frequency switching ripple noises can be designed uniquely by digital means and completely differentiated from the analog compensator’s single-pole low-pass filter in Figure 4(a).
Benefiting from the advantages of digital signal processing, a low-latency FIR ripple filter can be easily incorporated and all repetitive elements of ripple are totally rejected. All that remains are the non-periodic elements in the waveform, including transient steps with little or no delay. This results in more than 20dB of ripple reduction without a significant time delay, thus allowing higher gains and higher bandwidths.
Putting it All Together

Thermal performance, increased power density and electrical performances are the three main challenges faced by the POL power system designer for the latest FPGAs, processors, ASICs and memories used in telecom, datacom and industrial equipment. While there are a variety of methods to address these challenges, digital power modules offer an unprecedented combination of size and performance. Innovative digital power architectures combined with electromechanical advances reduce the traditional trade-offs faced by system designers, making it possible to get outstanding thermal performance, improved efficiency and transient response in a high power density form factor.

For more details about Intersil’s Power Module solutions, simulation tool and white papers click here.

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