The program is designed to boost the adoption of Microsemi’s RISC-V soft CPU product family utilizing RISC-V open instruction set architectures (ISAs).
Imperas’ Virtual Extendable Platform Kit provides a software simulation environment for the development, debugging and testing of software running on Microsemi’s RISC-V soft core. This environment, with improved controllability, visibility, repeatability and ease of automation, accelerates software development. This enables higher quality software, particularly for applications demanding reliability, safety and security. As the first commercially supported ISS for RISC-V processors, with debug integrated with SoftConsole, the kit is also an example platform running the FreeRTOS operating system. Customers can now choose commercially supported ISS for their software development tasks versus an open source, self-support-style ISS.
RISC-V, an ISA which is now a standard open architecture under the governance of the RISC-V Foundation, offers numerous benefits, including enabling the open source community to test and improve cores at a faster pace than closed ISAs. As the RISC-V intellectual property (IP) core is not encrypted, it can be used to ensure trust and certifications not possible with closed architectures. Portability is another benefit of the technology. For example, designers can begin development with Microsemi’s RISC-V core in its FPGAs and then move to an application-specific integrated circuit (ASIC) royalty-free.
Imperas – www.imperas.com
Microsemi – www.microsemi.com