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Eye on Standards:  Four 400G quandaries to look forward to

Eye on Standards: Four 400G quandaries to look forward to

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By eeNews Europe



In 400G Ethernet Effort Begins, John D’Ambrosia, Chair of the Ethernet Alliance and 400G Ethernet Group, said, "The key part is that this initial effort will spend significant time and energy on defining an architecture that will be flexible and enable future 400GbE implementations." He went on to say that, "diving into the technical details of each of these anticipated proposals will be part of the fun that awaits those ready for this project."

Back in 2007, the IEEE 802.3 High Speed Study Group realised that the data rate needs of networking and computing have been increasing at different rates (Figure 1); Moore’s Law scaling of 2x every 18 months for networking and 24 months for computing. So even though the 100 Gbit/sec spec is still somewhat incomplete, the technology is being rolled out and it’s not hard to see the demand for 400 Gbit/sec links coming on the horizon.

Figure 1. Core networking and server i/o demand projections from 2007 show that networking speeds are increasing at a faster rate than computing speeds. Source: IEEE 802.3 HSSG.

Among its goals, the 400G working group hopes to maintain backward compatibility, preserve Ethernet frame formatting, support OTN (optical transport network), and specify EEE (energy efficient Ethernet) as an option.

In addition to increasing the media access (MAC) rate by a factor of four over 100 GbE, the IEEE 802.3bs 400 GbE group plans include the following four quandaries.

Next; BER goes to 1E-13


Improving the maximum permissible BER (bit error ratio) by a factor of ten, from 1E-12 to 1E-13.

Improving BER performance is likely to require implementation of FEC (forward error correction) embedded in the PCS (physical coding / reconciliation sublayer) so that the FEC isn’t befuddled by more errors than it can correct in a span. The idea is that the PCS gearbox essentially stripes the data so that FEC isn’t faced with too many errors per frame even in the presence of bursts. The expectation of burst errors comes from the tendency of current state-of-the-art receiver DFE (decision feedback equalisation) to burst when it fails. Figure 2 shows a bathtub curve for a system operating at BER=1E-13.

Figure 2. Bathtub plot for a signal operating at BER = 1E-13.

Next; Single-mode and multi-mode fibre


Expect the standard to specify minimum of 100m over multi-mode fibre and 5 km over single-mode fibre, with many different configurations.

The idea is to support a variety of topologies so that different technology options can be implemented to reach 400 Gbits/sec. A single 400 Gbit/sec optical signal on one fibre carrying one wavelength is unlikely. Rather, the back-to-the-future trend of parallel lanes that preserve the advantages of serial data systems will continue to proliferate from 100 GbE (Figure 3).

That is, we should expect combinations of WDM (wavelength division multiplexing, i.e., multiple independent wavelengths carried on a single fibre) and multiple fibre configurations. Since WDM performance is limited on multimode fibres, expect WDM single-mode fibre and parallel multi-mode fibre scenarios in almost every permutation of 25 Gbit/sec, 50 Gbit/sec, and 100 Gbit/sec links that can combine to 400 Gbit/sec. The permutations may range from from the full-blown, long-reach, four wavelengths at 100 Gbits/sec on one single-mode fibre, to a stop-gap, early design of 16 separate multimode fibres each carrying a 25 Gb/sec signal: and everything in between.

Figure 3. Two of many possible 400G topologies.

Next; Channel options…


Electrical chip-to-chip and chip-to-module channel options

The limitations of installed and seemingly immoveable standard FR4 PCB (flame retardant type-4 printed circuit board) infrastructure will not be replaced until…ever. Because typical intersystem communications over backplanes and midplanes require electrical signalling over distances up to about 100 cm, technology will drive design choices.

Can four 100 Gbit/sec electrical signals make it over 100 cm of PCB? Seems impossible, right? The ISI (inter-symbol interference) would present a gargantuan receiver equalisation challenge. But we heard this argument when we went to 10 Gbits/sec and we heard it again in going to 25 Gbits/sec. D’Ambrosia points out, "The industry should consider how many times it has written off copper, only to see a copper-based solution emerge. Copper could be considered the true phoenix of the industry."

It’s probably reasonable to look to OIF-CEI (Optical Internetworking Forum’s Common Electrical Interface working group) for short reach 400G electrical options. Unless bulky pseudo-parallel 16×25 Gbit/sec traces (Figure 4) are used, it’s likely that flex circuits and micro-coax will have to be considered.

Figure 4. Possible chip-to-module short-reach 400G topology starts with 16×25 Gbit/s lanes.

Next; goodbye, NRZ?


NRZ (non-return-to-zero) modulation is likely to become a fond memory

There will be no more hiding from PAM (pulse amplitude modulation), DMT (discrete multi-tone modulation), or ENRZ (ensemble non-return-to-zero) data formats. Figure 5 shows NRZ modulation (top trace) and PAM4 modulation (bottom trace).

Figure 5. Comparison of NRZ and PAM4 signals at the same data rate.

Surely somewhere around 50 Gbits/sec we’ll reach the point where multi-moding kicks in and NRZ fails. At this point, I believe we’ll have to turn to PAM4 or some other clever modulation format that can reduce the signal bandwidth without affecting the data rate. I say that despite what Tom Palkert from Luxtera said at OFC 2014.

At least one of us (me, for example) hopes that trying to get 50 Gbit/sec, 100 Gbit/sec, or even 400 Gbit/sec signals from chip-to-chip will bring silicon photonics to the mainstream!

What do you think will be the biggest hurdle in advancing from 100 Gbits/s to 400 Gbits/s?

When do you think silicon photonics will go mainstream?

Do you think IEEE should put the wraps on 100GbE before moving on to 400GbE?

Also see;

When will PAM4 take over from NRZ?
The next generation’s modulation: PAM-4, NRZ, or ENRZ?
Reducing test costs for silicon photonics

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