Failure mode enables single transistor for neuromorphic AI chips
Researchers in Singapore have tapped a phenomenon usually regarded as a failure mechanism to produce a single transistor that slashes the complexity of neuromorphic AI chips.
Implementing neurons and synapses with traditional silicon transistors in neuromorphic chips requires at least 18 transistors per neuron and 6 per synapse. Instead, the team at the National University of Singapore (NUS) found a way to reproduce the electronic behaviours characteristic of neurons and synapses by setting the resistance of the bulk terminal of a MOSFET to a specific value to produce a physical phenomenon called impact ionisation.
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Operating the device on the verge of punch-through conditions while adjusting the resistance of the bulk connection to ground generates a current spike very similar to the activity in an electronic neuron.
This impact isolation is usually considered a failure mechanism in silicon transistors, but the team, led by associate Professor Mario Lanza from the Department of Materials Science and Engineering at the College of Design and Engineering, has managed to control it and use it for a new type of neuromorphic transistor cell, the NS-RAM.
By setting the bulk resistance to other specific values, the transistor can store charge in the gate oxide, causing the resistance of the transistor to persist over time, mimicking the behaviour of an electronic synapse. This means that the transistor can operate as a neuron or synapse by selecting the appropriate resistance for the bulk terminal.
In neuron mode, the two-transistor cell emulated leaky-integrate-and-fire neural behaviour and adaptive frequency bursting, with a high switching slope (below 10 mV/dec), a dynamic range over 1000, high endurance of over 10 million cycles and competitive energy efficiency with a firing energy down to 415 pJ/μm.
When operated as a synapse, a single transistor in the floating-bulk configuration could be programmed with at least six synaptic weights that were stable over time with high endurance of over 100,000 cycles.
“Considering that each artificial neural network contains millions of electronic neurons and synapses, this could represent a huge leap forward in computing systems capable of processing much more information while consuming far less energy,” says the team, which has designed a cell with two transistors on 180nm process.
This Neuro-Synaptic Random Access Memory (NS-RAM) cell allows switching between the neuron and synapse operating modes to provide flexibility for neuromorphic AI chip designs. This cell allows both functions can be reproduced using a single block without the need to dope the silicon to achieve specific substrate resistance values.
“Other approaches require complex transistor arrays or novel materials with uncertain manufacturability, but our method makes use of commercial CMOS (complementary metal-oxide-semiconductor) technology, the same platform found in modern computer processors and memory microchips,” said Lanza.
“This means it’s scalable, reliable and compatible with existing semiconductor fabrication processes. Once the operating mechanism is discovered, it’s now more a matter of microelectronic design.”
Synaptic and neural behaviours in a standard silicon transistor
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