Fan-out wafer level packaging fills gap to 3D, says Yole
Fan-Out Wafer Level Packaging (FOWLP) started volume commercialization in 2009/2010 and started promisingly, with initial push by Intel Mobile. However, it was limited to a narrow range of applications – essentially single die packages for cell phone baseband chips – reaching its limit in 2011. In 2012 big fab-less wireless/mobile players started slowly volume production after qualifying the technology.
It faced strong competition from other packages such as wafer-level chip scale packaging (WLCSP) in 2013/2014. Intel Mobile also backed off from the technology, and the main manufacturers reduced their prices in 2014, creating a transition phase with low market growth.
Today, the market is worth almost $200M and the market research firm anticipates 30% CAGR is in coming years. One of the key factors driving this is the arrival of 2nd generation FOWLP. More customers are also being convinced, a wider range of potential applications reached, and technology qualifications started during the transition phase completed by strong fabless players.
What can explain such great potential?
Primarily, mobile customers have high expectations of miniaturization and higher integration while keeping costs low. This leads naturally to WLP for cost and performance and system-in-package (SiP) solutions for integration and functionality. FOWLP has proven its ability to reach these targets. Its small form-factor and low cost potential shown in the 1st generation are now enhanced with high-integration capability of the 2nd generation as shown in figure 2.
Benefiting from the delay in introducing 3D through-silicon via (TSV) architectures, FOWLP is currently seen as the best fit for the highly demanding mobile/wireless market and is attractive for other markets focusing on high performance and small size.
Yole’s report describes the different strategies and products of each player involved in FOWLP, from the main outsourced assembly and test companies, like STATS ChipPAC and Nanium, to foundries like TSMC. It also provides detailed roadmaps and supply chain analysis, explaining the complexity and the trends already showing potential in this highly promising market.
Similarly to FOWLP, Embedded Die in Substrate is an approach getting the attention of potential customers, as it brings many advantages. The embedding allows a smaller form-factor, and it can be done using a mature manufacturing chain, providing low costs. The approach also offers good thermal performance, high integration capability and low inductance thanks to shorter connections.
The Fan-Out and Embedded Die: Technologies & Market report gives an overview of players involved in embedded die packages. It describes the strategies they’re hoping will overcome technical issues such as yield, resolution and reliability and their choices of business model to enter the semiconductor packaging market with.
Visit Yole Développement at www.yole.fr
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