Fast RF ADCs/DACs integrated with FPGA for programmable 5G designs

Fast RF ADCs/DACs integrated with FPGA for programmable 5G designs

New Products |
By Graham Prophet

The digital processing in such designs has typically been performed in advanced FPGAs. However, such architectures can be power hungry, not least because very high data volumes must be transferred from sampling front-ends to the processing matrix, at very high speeds, which consumes power.


Xilinx has been promoting its “all-programmable” concept for some time, with products such as its Zynq range, which combine FPGA hardware (programmable by configuration) with embedded processor cores (software programmable) – hence, all-programmable. Now, it has added high speed data conversion functions, integrated on-chip, to that mix. Having the sampled data on-chip offers power savings over driving that data over chip-chip lines.


Xilinx is presenting this move as a “disruptive integration and architectural breakthrough

for 5G wireless, with RF-class analogue technology.” Its RFSoC devices will enable 50-75% power and footprint reduction for 5G massive MIMO radio and millimeter-wave wireless backhaul, the company says.


The RF-class analogue technology is integrated into Xilinx’ 16nm all-programmable MPSoCs, to make All Programmable RFSoCs. Xilinx notes that, “Large scale 2D antenna array systems will be key to the increase in spectral efficiency and network [density increases] needed for 5G. Manufacturers must find new ways to meet stringent requirements for commercial deployment. With the integration of high performance ADCs and DACs in an All Programmable SoC, radio and wireless backhaul units can now meet previously unattainable power and form factor requirements, while increasing channel density. RFSoC devices allow manufactures to streamline design and development cycles to meet 5G deployment timelines.”


The integrated 16nm-based RF data conversion technology includes:

– Direct RF sampling for simplified analogue design, greater accuracy, smaller form factor, and lower power

– 12-bit ADCs at up to 4 GSPS, high channel count, with digital down-conversion

– 14-bit DACs at up to 6.4 GSPS, high channel count, with digital up conversion


“Integrating RF signal processing into All Programmable SoCs enables our customers to dramatically change their systems architectures,” said Liam Madden, Corporate Vice President, FPGA Development and Silicon Technology at Xilinx, adding, “This will effectively enable our 5G customers to commercially deploy highly differentiated, large-scale, massive-MIMO and millimeter-wave backhaul systems.





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