Agile Analog in Cambridge has launched a complete set of analog functions for developing IoT chips.
The six IP blocks wrap round the customer’s choice of processor core and memory to provide all the vital analog functions required, from interfaces and sensors to security and power management. This allows developers to use cores from ARM or RISC-V suppliers such as Codasip or SiFive.
For example, the Power block could contain several agileLDOs to provide the necessary internal voltage rails together with agilePOR to ensure the SoC only starts when stable voltage rails are present. The IC Heath and Monitoring block monitors the SoC die temperature with the agileTsense whilst the agileIR DROP monitors long term aging effects.
The Security Protection block uses the agileVGlitch and agileTsense IP blocks to monitor for potential side channel attacks using voltage and temperature manipulation. A Radio Interface can also support low power Bluetooth or LoRa wireless links.
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Agile Analog’s Composa tool enables these blocks to be generated and validated for whatever process and node that the customer requires. It can rapidly regenerate a solution should this change enabling easy portability between foundries and processes.
The six blocks are:
- SoC/ASIC Security Protection with voltage glitch sensor and temperature sensor
- Sensor Interface with 8/10-bit SAR ADC, 8/10-bit DAC, and low power programmable comparator
- Always on Block with low power RC oscillator, low power bandgap, compact digital standard cell library, low power programmable comparator and power on rest.
- IC Health and Monitoring with temperature sensor and IR drop sensor.
- Power with low dropout regulator, power on reset, IR drop sensor and low power bandgap.
- Radio Interface with 8/10-bit SAR ADC, 8/10-bit DAC, RC oscillator and low dropout regulator.
- “We call these our Foundation IP as they provide all the functionality needed for an IoT design. Naturally, customers can mix and match whichever blocks they require for their design and adjust the number of each IP within it,” said Barry Paterson, new CEO of Agile Analog.
“Effectively this provides a foundation toolkit for all the analog parts that a design might possibly need to fast track, simplify and re-risk the design process,” he said. “We have included all the features and functions that a customer would require so that they can select exactly what they require from the set without worrying that they missed something vital.
“Importantly, the high level of customer support that we provide ensures easy and perfect integration unlike some rivals who just sell the analog blocks and leave customers to figure out how to use them. Also, customers have the security of knowing that, by using IP from one supplier, all our IP blocks have been fully tested for compatibility with every other one of our blocks.”
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The IP is fully supported for the design phase to ensure that it meets the Power, Performance and Area (PPA) requirements of the design. This also includes supporting the integration of the IP into the overall design. This is made easier by the IPs within the blocks being internally interconnected and that the blocks have external interfaces so that they look like digital blocks and can drop into the digital design flow.
All the major foundries are supported including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and manufacturers.
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