Faster architecture accelerates Tensilica DSP

Faster architecture accelerates Tensilica DSP

New Products |
By Christoph Hammerschmidt

A deeper 13-stage processor pipeline and a system architecture specially designed for large local memories allow the Vision Q6 DSP a maximum clock frequency of 1.5 GHz and a typical clock frequency of 1 GHz in 16 nm with the same floor plan area as the Vision P6 DSP.

Architecture of the new Tensilica Vision Q6 DSP

Other Vision Q6 DSP features include:

  • The extended DSP instruction set requires up to 20 percent fewer cycles than the Vision P6 DSP for embedded vision applications/kernels such as optical flow, transpose and warpAffine as well as frequently used filters such as Median and Sobel.
  • Double system data bandwidth with separate master/slave AXI interfaces for data/commands and multi-channel DMA enables higher memory bandwidth in vision and AI applications. In addition, latency and overhead can be reduced in connection with task switching and DMA setup
  • Backwards compatible with Vision P6 DSP, so customers can preserve their software investments through easy migration
  • Optional vector floating point unit (VFPU) also supports FP16 (Half Precision Floating Point)

The Vision Q6 DSP supports AI applications developed in Caffe, TensorFlow and TensorFlowLite frameworks with the Tensilica Xtensa Neural Network Compiler (XNNC). The XNNC maps neural networks into executable, highly optimized high-performance code for the Vision Q6 DSP using a set of optimized library functions for neural networks. The Vision Q6 DSP also supports the Android Neural Network (ANN) API for AI acceleration in Android devices.

Selected customers have already integrated the Vision Q6 DSP into their products. From now on the product is available for all customers.

Further information:

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