FD-SOI breakthrough boosts performance

FD-SOI breakthrough boosts performance
Technology News |
CEA-Leti and Dolphin Design have developed a new approach to FD-SOI that boosts operating frequency by 450 percent with a 30 percent power reduction
By Nick Flaherty

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CEA-Leti and Dolphin Design have developed an adaptive back-biasing (ABB) architecture for fully depleted silicon on insulator (FD-SOI) chips that can be seamlessly integrated into an industrial design flow. This enables a tiny regulator that provides stable control of the ABB in a chip.  

FD-SOI allows the biasing of the transistor’s body that acts as a back gate. Unlike conventional bulk technology, FD-SOI enables a wide voltage range of the body bias. This permits compensating for process, voltage, and temperature (PVT) variations by controlling the threshold voltage.

For example, in switch operations, when the switch is on, the body bias is changed to reduce the on-resistance by reducing threshold voltage and allowing more current to pass. That accelerates the circuit. In the off state, the body bias is changed to raise the off-resistance by increasing the threshold voltage, consequently reducing the leakage current. This allows designers to increase the operating frequency or reduce the leakage power. 

The new ABB technique also allows a design to maintain a targeted operating frequency over a wide range of operating conditions such as temperature, manufacturing variability and supply voltage. This boosts the performance and yield of designs in current 22nm FD-SOI process technology.

“The ABB development is a breakthrough for FD-SOI technology because it shows the first-ever results depicting the enhancement in the circuit performance after using ABB, and it will help increase performances and yields in FD-SOI designs,” said Gaël Pillonnet, a CEA-Leti scientist and an author of the ISSCC paper. The ABB regulator measures just 0.021 mm² in 22nm FD-SOI. 

The ABB block is being commercialized by French design house Dolphin Design based on CEA-Leti’s proof of concept.

Next: Commercialising FD-SOI design block


“The performance of our ABB IP is state of the art and show the compensation of the variations across process-voltage-temperature (PVT) conditions on a representative number of samples, enabling the usage of this solution in industrial products,” said Andrea Bonzo, IP program manager at Dolphin Design.

“Previous efforts in this technique have reported only limited numbers of chips that perform as intended. With our technique, a large number of chips are shown to work properly. ABB is versatile and can be used to drive a large digital area without any limitation for any FD-SOI technology.”

With this new architecture, the ABB area is relatively small compared to the application design, and in both area and power it allows the application design to maintain its targeted frequency with a relatively low overhead.

www.leti-cea.com

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