FD-SOI gets compact standard model for circuit-simulation

FD-SOI gets compact standard model for circuit-simulation

Technology News |
CEA-Leti has announced that its compact simulation model for FD-SOI technologies, L-UTSOI, has been selected as a standard by the Compact Model Coalition (CMC), a working group composed of the major semiconductor companies and part of the Silicon Integration Initiative (Si2).
By eeNews Europe


L-UTSOI was extensively proven by the industry and its standardization will ensure long-term access and maintenance in EDA tools for FD-SOI designers. Available to coalition members now, it will soon be implemented in major versions of circuit-simulation software, and its source code will be released publicly in June 2021.

Once a new or enhanced chip is designed, it must be simulated prior to entering the expensive manufacturing phase. This proof-of-concept step relies on compact models that are expressed through a set of equations implemented in a form ensuring accuracy, robustness and numerical efficiency. Such compact models are approved and supported by the standard-setting arm of Si2, the CMC, which is an international working group focused on standardizing SPICE device models.

Standard models are developed by the world’s leading SPICE-model experts. They are used by designers working at the most advanced fabless semiconductor companies, integrated circuit foundries, and integrated device manufacturers. Implemented in the industry’s top versions of circuit-simulation software and duly qualified, standard models give designers the assurance that their integrated circuits will perform according to the design specifications.

Fully Depleted Silicon-on-Insulator (FD-SOI), which was pioneered by CEA-Leti in 1992, is a widely used approach to semiconductor manufacturing in which microelectronic devices are built on wafers coated with a silicon thin film over an insulating buried-silicon-oxide layer. An FD-SOI transistor is a four-pin transistor with a back-gate that allows tuning the device in a low- leakage and low-power operating regime or higher-performance operating regime.

This unique capability offered by FD-SOI technology allows the fabrication of smaller, faster and denser chips than standard complementary metal-oxide semiconductor (CMOS) technology. FD-SOI devices are widely used in wearable electronics, automobiles, as well as Internet of Things networks.

L-UTSOI is derived from the Leti-UTSOI compact model, which has been implemented in circuit-simulation software and used in industrial process design-kits for several years.

“The selection of L-UTSOI as a Si2-CMC standard model ensures that it will be supported as long CMC industry members use it”, said Thierry Poiroux, head of CEA-Leti’s Simulation and Compact Model Laboratory.

“This is of paramount importance for large chip makers who will use this model in the future. With a standard model, they are assured that a team of model developers is able to take care of the model improvements and/or bug fixes they need during the whole lifetime of their technology. It also positions CEA-Leti among the few compact-model developer teams able to develop and support a standard model.”

Leti – www.leti-cea.com

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