Final test interface accelerates time-to-market for mobile devices
Traditional solutions for testing 16 or more complex devices require sophisticated, custom device interface boards (DIBs) which are difficult and time consuming to design, manufacture and release into volume production. These challenges add schedule and cost risk to new applications processors, RF and power management device programs.
The SOC TIU’s innovative design simplifies high site count solutions by grouping tester resources and segmenting DIBs into multiple exact copies, enabling the reduction of load board design and fabrication time by more than 40% and debugging and correlation time by more than 60%, to deliver faster time to volume production. Customer results have shown that the SOC TIU also provides improved signal distribution and better site-to-site correlation for testing devices at 16 sites or more.
The SOC TIU allows users to apply more than 8,000 UltraFLEX digital and analog resources to their most challenging devices under test. When combined with typical parallel test efficiencies of greater than 99% users are able to meet the cost and schedule requirements of the mobile device market.
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