Find IGBT degradation through power cycling

Find IGBT degradation through power cycling

Technology News |
By eeNews Europe

Dissipated heat in a junction is one of the major effects that can influence the reliability of die-attach materials used in an IGBT’s chip. Power cycling tests are ideal to mimic the lifecycle of a module because the number of switching cycles corresponding to an IGBT module can be predicted based on the target application.

This article describes an experiment in which we conducted thermal transient tests from one steady-state to another to determine cause of failure for a small sample of IGBTs. These types of tests may support proper re-design of the physical structure of the module, and if needed, it can also serve as an input for thermo-mechanical stress simulations.

Our aim was to investigate the common failure modes emerging in current IGBT modules using a replicable process. Although the tests weren’t done in a high-enough enough volume to predict lifetime, they let us examine the degradation process. We started by performing conducted thermal-transient tests on the samples. Trial measurement showed that the thermal transient of the device from steady state to steady state was 180 s. The hot steady state was achieved using 10 A of driving current on the device, which was switched to 100 mA sensor current when we started to acquire data.

Figure 1 shows the thermal transient function that describes the initial "healthy" status of the sample. This curve and the corresponding structure function were used as a basis for calibration of a detailed numerical representation of the package. Structure functions are direct models of one-dimensional, longitudinal heat-flow. In many frequently used 3D geometries, structure functions are direct models of the "essentially" 1D heat flow, such as radial spreading in a disc (1D flow in polar coordinate system), spherical spreading, conical spreading, etc. As such, structure functions can be used to approximately identify geometry/material parameters. The structure functions are obtained by direct mathematical transformations from the heating or cooling curves. These curves may be obtained either from measurements or from the simulations of the detailed structural model of the heat-flow path.

Figure 1. Thermal transient response of the studied IGBT prior to subjecting it to power and thermal stress.

Creating a thermal simulation model

We then built and verified a detailed 3D model of the module so that we could analyze the temperature distribution inside the structure. The geometric parameters were measured after all devices failed and the module has been disassembled. The model layout is shown in Figure 2 (the cross-section of the structure is shown in Figure 3).

So that we could be assured that the simulation model would behave the same way as the real device, we adjusted the material parameters until the structure functions obtained from the simulated transient results fitted the experimentally derived structure function. This process required a number of iterations.

Figure 2. Layout of the simulation model.

Figure 3. Cross-section of an IGBT module shows the bond wires attached to the device.

The base-line model, which we created based on the measured geometry and the best guess of the material parameters, showed a significantly different thermal transient behavior than the real device. Such discrepancies can be eliminated by calibrating the model, successively refining the model data. We did this by fitting the structure functions obtained from the thermal transient simulation of the model (red curve in Figure 4), to the structure functions generated from measurements of the real device (blue curve).

Figure 4. Simulation result of the baseline model shows an offset between simulated devices (red) and physical devices (blue).

Next, we began calibrating the device by fitting the internal features of the package. We then went outward from the package in the direction of the heat flow path, fitting successively the thermal capacitance and thermal resistance values of the different regions. To adjust the die capacitance properly, we made sure the physical dimensions of the die were correct and the area of the heat sources was set properly. In this case, we needed to increase the heated area until the capacitance values at the die region overlapped each other on the structure function.

Then, we needed to make sure that the thermal resistance of the ceramics layer was set to the appropriate level. With the increase of the thermal conductivity of the ceramics, the length of the corresponding thermal resistance section on the structure function could be reduced to achieve a new fitting section. After that, we set the bottom copper layer and the TIM (thermal interface material) between the device and the cold-plate to the appropriate thermal conductivity level for a proper match of the curves Figure 5.

Figure 5. Structure function of the simulated (blue) and measured (red) transients after model calibration shows a tight fit.

Running the device in the power tester

As soon as we recorded the initial status of the IGBT’s thermal structure, we exposed the device to reliability tests so we could assess its long-term behavior. We fixed the selected IGBT module to a water-cooled cold plate with a thermal pad. The thermal pad has poor conductivity compared to most of the thermal pastes and gels, but it showed great thermal stability in earlier experiments. Thus, it didn’t affect the measured results. The cold-plate temperature was set to 25°C.

The module under test contained two half-bridge modules, that is, four IGBTs. The gates of the devices were connected to the drains, and the half-bridge modules were powered using separated driver circuits (see Figure 6). All IGBTs were connected to separate channels of the thermal transient tester equipment.

Figure 6. We used these electrical connections of the IGBTs for power cycling and thermal transient measurements.

We decided to apply a 100°C temperature swing on the device under test to accelerate the power-cycling process. This value was selected so that the maximum junction temperature would be 125°C, which is device’s allowed maximum. We maximized the power applied to the module to reduce the cycle time and selected the appropriate timing to achieve the target 100°C temperature swing. The IGBT module can handle currents up to 80 A, but because of the high voltage drop on the devices, the power rating became the limiting factor. Based on previous trial measurements, 25 A was selected as heating current.

We needed to use 200 W of heating power for 3 s to heat the chips to 125°C. The cooling time was set to ensure that the chips would have sufficient time to cool, and the average temperature wouldn’t change during the tests. The timing diagram and the temperature profile are shown in Figure 7.

Figure 7. Switching diagram of heating power and junction temperature during power cycling shows the expected thermal delay.

The applied heating current and timing remained constant during the whole testing process regardless of the changing voltage drop or increasing thermal resistance. The cooling transient of the devices was recorded in every cycle that was made possible to monitor the junction temperature change continuously. After every 200 cycles, a full-length transient measurement was performed using a 10-A heating current to check the structural integrity of the heat flow path.

Failed gate oxide, not bond wires

In our experiment, we continued the power cycling until the device totally malfunctioned (short circuit or open circuit), which was our failure criteria. Out of the four IGBT devices tested, one device failed significantly earlier than the others, after just 10,158 power cycles (Figure 8). This premature failure was probably caused by incorrect mounting in the cold-plate or some random error. The other three devices, samples 0, 1, and 2, showed similar behavior and failed after 40660, 41476, and 43489, respectively.

Figure 8. One IGBT device failed significantly earlier than others.

After all the IGBTs failed, we disassembled the modules and examined the condition of the chips and bond wires. Figure 9 shows an image of one of the chips, illustrating that several bond wires broke during the tests and an area on the chip surface was burned, which was probably caused by the arc when a wire detached while high current was applied.

Figure 9. Photo of the device shows broken bond wires and burnt chip surface.

Failure from overheating

Despite the obvious defects of the bond wires, the broken bond wires did not cause failure of the devices. All of the chips failed because of overheating and damage to the gate oxide. These effects could later be examined and tracked using electrical tests: the cracking of the bond-wires was indicated by the increase of the VCE (collector-emitter) voltage, and the damage of the gate oxide resulted in the increase of the IG, gate leakage current. When designing IGBT power cycler equipment, these parameters ought to be measured.

The joints between the substrate and the baseplate and the die-attach also need to be investigated for us to understand the source of the overheating, which is why we needed the calibrated simulation model. Figure 10 shows the temperature distribution of two adjacent IGBTs at the end of the heating period simulated using the calibrated detailed model. The thermal coupling between the adjacent chips was negligible; thus, each chip could be investigated individually.

Figure 10. Simulated temperature distribution of one half-bridge module after 3 seconds shows little thermal coupling.

Because of the short heating time, the maximum temperature elevation of the substrate-base plate joint was 71°C, but the die-attach temperature increased by more than 100°C. This result indicated that the most vulnerable point of the structure was the die-attach material.

The periodically measured thermal transients allowed us to generate structure functions corresponding to various number of applied power cycles. Figure 11 shows the effect of the generated power cycles on the structure functions corresponding to every 5,000th cycle. After the first capacitive step, the flat region corresponded to the die-attach material. The structure was stable until 17,000 cycles; however, after that point, the degradation of the die-attach material was obvious, and its resistance increased continuously until the device failed.

Figure 11. Structure functions of sample 0 corresponding to control measurements at various time points show different failure points.

As shown in Figure 12, we divided the thermal resistance of the die-attach layer that was read by the initial junction-to-ambient resistance of the system and plotted it as a function of power cycles. This calculation confirms that the degradation of this layer started soon after 15,000 cycles. The heat-flow path changed so dramatically because of the significant change in the die-attach material that it was impossible to investigate the latter structural elements. However, degradation in the latter sections could be reasonably expected as well, but they would be negligible compared to the problem with the die-attach material.

Figure 12. Thermal resistance of the die-attach layer relative to the junction to ambient thermal resistance in the initial state show the point of failure.

After approximately 20,000 cycles, the effect of the die- attach degradation was significant, and in about 10,000 cycles, the total junction-to-ambient thermal resistance of the sample doubled as a result of the cycling. After 30,000 cycles, we were unable to determine the exact thermal resistance of the die-attach layer because of the changes in the heat spreading path.

This work was partially supported by the 288801 SMARTPOWER integrated project of the Framework 7 Program of the EU. This information was originally presented at the Electronics Packaging Technology Conference.

About the author

Andras Vass-Varnai obtained his MSc degree in electrical engineering in 2007 at the Budapest University of Technology and Economics. He started his professional career at the MicReD group of Mentor Graphics as an application engineer.

Andras managed technically the EU-funded Nanopack FP7 project on behalf of Mentor Graphics, resulting in the development of DynTIM, the Mentor Graphics thermal interface material (TIM) measurement solution. Currently, he works as a product manager responsible for the Mentor Graphics thermal transient testing hardware solutions, including the T3Ster product. His main topics of interest include thermal management of electric systems, advanced applications of thermal transient testing, characterization of TIM materials, and reliability testing of high power semiconductor devices.

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