FinFET’s father forecasts future

FinFET’s father forecasts future

Technology News |
By Julien Happich

Hu described new transistor concepts that could fuel the chip industry for decades in a talk at the annual Synopsys Users Group event here. His presentation came a day after the company’s chief executive expressed similar optimism, citing progress in software design tools.

“I really mean it when I say this industry goes on another 100 years, in part because there are no alternatives and the world needs us,” Hu told an audience of several hundred chip designers here.

“We all know but don’t like to say out loud that transistor size reduction is a game that has an end and we are racing to that end,” but that doesn’t mean the end of the semiconductor industry and the high tech sector build on top of it, Hu said.

  Chenming Hu sees a long future for thin-body transistors like FinFETs and FD-SOI. (Images: Synopsys)

The negative-capacitace transistor (NC-FET) is one of the latest and most significant concepts to emerge from labs at the University of California at Berkeley where Hu is a professor. Hu and colleagues showed work on a 30nm NC-FET made in hafnium zircon dioxide and using a novel 5nm ferroelectric layer.

“Essentially it puts a voltage amplifier into the dielectric…the idea is you get the same performance at lower Vdd,” Hu explained.

The design could help engineers reduce Vdd to levels below 0.3 V, overcoming limits that could pave the way to decades of new devices.

The NC-FET has “not been on anyone’s radar because we’ve been developing it on a shoestring but now we see it’s promising and we’re looking for support,” said Hu. “There are orders of magnitude more money going into spintronics than NC-FET, I think we are the only ones in the industry working on it,” he said.

Recently, Berkeley set up a new center to focus on the NC-FET. Intel and TSMC joined, paying $140,000 each. “If we could get a handful of members we could do great things, and that’s still smaller than a typical government contract,” he said.

Separately a handful of companies including Globalfoundries, Samsung, Synopsys and TSMC joined the Berkeley Device Modeling Center that creates BSIM models that translate physical fab data for software design tools.

“We are preparing the compact models for new devices wherever they come from free of royalty, but nothing is really free,” Hu said noting the models for FinFETs took 11 years work from more than a dozen researchers.

NC-FETs add a novel ferroelectric layer to
a conventional looking transistor.


In parallel with the NC-FET, researchers are developing 2D semiconductors using layers of a dozen candidate materials that could be deposited at the thickness of a molecule or even an atom. “One layer of this material makes a perfect crystal that would be the ideal thin-body material eventually, and we would not need to worry about quantum effects,” he said.

“I’m excited about 2D semiconductors because whether used for memory or logic monolithic multilayer integration…layers of circuits separated by oxides…using self-assembly of atoms such as molybdenum…that’s really exciting, and a good interface for us to continue our work,” he said.

Hu showed research first presented in December of 2D NMOS and PMOS devices deposited on a single layer of silicon and “folded in on itself.” The technique showed a 45% reduction in transistor size.

2D semiconductors could be built from layers just one molecule or atom thick.

The new designs are essentially variations of the kind of thin-body devices used in today’s FinFET and fully depleted silicon-on-insulator (FD-SOI) processes. Such designs, using a variety of new materials, will have a long life, Hu predicted.

Tall fins will likely continue to be popular given the performance advantages they carry. And future processes are likely to mix fins of different heights to optimize processes for specific uses, he said. “I can foresee thin-body designs through to the end of lithography,” he added.

Today’s FinFET and FD-SOI structures “could go to gate-all-around or pillar or wires, depending on which is most economical to fabricate…it’s all about cost versus performance,” he said.

Hu was less optimistic about tunneling transistors and spintronics. The on-current for tunneling transistors is an order of magnitude or more lower than today’s devices, making them only suitable for use in Internet of Things nodes.

Spintronics requires a whole new tool set for logic, making it impractical. “Our design infrastructure is so precious…it would be really hard to introduce a transistor that used totally different concepts,” Hu said.

After industry maturation comes rejuvenation, said de Geus.

It’s a challenging time in chip design. As semiconductor companies consolidate to handle the rising cost of making chips, design starts and sales of EDA seats are both “flattish” said Synopsys’ chief executive Aart de Geus in a brief interview with EE Times. He cited compound annual chip industry revenues of 4.4% and growth “last year and this year closer to zero.”

Nevertheless, de Geus was as upbeat as Hu in a talk focused on his company’s advances in EDA that opened the event.

“I understand the industry is under economic stress and changes but we are on the edge of a wave that will change the world again…The opportunity to make everything smart is huge and will change the world,” he said.

He quipped that IoT could stand for Immensely Optimistic Thinking, because “it’s insufficient to drive semiconductor volumes, but great for connecting us to physical attributes of the real world.” Nevertheless, “if we can deliver another 10-100x advances in performance over power it will have enormous ramifications that are unpredictable,” he added.

Despite early teething problems with FinFETs, Synopsys has seen more than 50 test chips tape out in 14/16nm processes. For example, a high-end car infotainment SoC from Renesas used a full Synopsys flow in TSMC’s 16FF+ process.

Among other advances he cited:

Test algorithms rolling out this summer that will speed runtime and reduce test vectors 25%

A 14nm networking SoC that reduced wire length 17% using IC Compiler II

A 7nm test chip that routed 99% of end points within 1% of PTSI with ICC II

ECO closure in eight hours using one Prime Time system for a design with 50 million instances and 20 scenarios

A new verification algorithm called Cheetah that adapts to the CPU and GPU cores on a processor to speed up work five-fold at the RTL level.

De Geus pointed to the growing security business Synopsys is building around its acquisition of companies including Coverity.

“This is already for us a $100 million business so it’s not a hobby, it’s a key direction,” he said. “Every IoT device is the equivalent of a kitchen window in a bank…the fact is there are kitchen windows in all the software in the world,” he said.


About the author:

Rick Merritt is Silicon Valley Bureau Chief at EE Times

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