FinFETs-on-SOI able to double battery life
Professor Asen Asenov, CEO of GSS, has written a series of blogs on the company’s website discussing simulations of FinFETs that use the company’s simulation tools. A starting point was shape of Intel’s FinFETs in a 22-nm bulk silicon process. The simulations are performed using the company’s Garand statistical 3-D TCAD simulator. He came to the conclusion that Intel may find it necessary to move to FinFET-on-SOI to shrink its process below 22-nm and that foundries yet to introduce FinFET processes would be advised to pay attention.
In May GSS performed simulation making use of newly acquired information that what Intel calls tri-gate transistors, are in fact trapezoidal, almost triangular, rather than rectangular in cross-section. In June GSS pointed out that rectangular FinFET structures have superior performance and that by opting for slope-sided fins Intel is missing out on some performance. Professor Asenov suggested that adopting FinFET on SOI wafers might make for the easier production of rectangular fins of a pre-determined and non-varying height.
In his latest blog Professor Asenov has conducted a series of simulations that compare rectangular FinFETs of different gate lengths and widths on bulk and SOI. The FinFETs are all roughly compatible with a 20-nm channel length process node. The consclusion is that FinFET-on-SOI is marginally better than FinFET-on-bulk in terms of drive current but a lot better in terms of leakage current.
Figure 1 shows that the SOI FinFETs deliver on average 5 percent higher drive current than bulk FinFETs. The SOI advantage tends to diminish with fin width and gate length.
Figure 2 shows that SOI FinFETs deliver between half and 30 percent of the leakage current of the same dimensioned FinFETs on bulk silicon. This could more than double battery life in mobile phones, Professor Asenov points out. Here the advantage of SOI FinFET decreases with decreasing gate length but increases and as fin width reduces.
rofessor Asenov pointed out that Intel’s triangular FinFETs are themselves some way behind the performance of these idealized rectangular cross-section FinFETs. It is thought that Intel has adopted the triangular cross section because it simplifies process steps for laying down and etching high-k gate insulator materials.
Researchers from GSS and the University of Glasgow published a paper at the International Electron Devices Meeting of 2011 that dealt with FinFETs implemented in SOI wafers and how they could meet the low statistical variability requirements of 11-nm CMOS. Professor Asenov said that GSS has been working with IBM.
For further information see: Professor Asenov’s July blog.
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