Finnish consortium tapes out multicore RISC-V edge AI IoT chip

Finnish consortium tapes out multicore RISC-V edge AI IoT chip

Business news |
By Nick Flaherty

The Finnish SoC Hub consortium has taped out its first system on chip design for IoT and Edge AI applications.

The Ballast chip is the first in a series of three chips to be manufactured by TSMC in a 22nm Ultra Low Leakage process for IoT and Edge applications. Ballast contains several different RISC-V CPU cores, a Digital Signal Processor, AI accelerator, sensor-like interfaces and an extension interface to FPGA. A full software stack – including drivers, software development tools and chip debugging support – has also been implemented and the chip supports both real-time operating systems and Linux simultaneously.

The project partners will focus next on improving the design, automation and performance of the SoC. The first of the three chips to be developed by the consortium will be ready for deployment in early 2022.

The Finnish SoC Hub aims to boost SoC design skills in Europe and to enhance Finland’s competitive position. The SoC Hub initiative, launched last year, is coordinated by Tampere University and Nokia but the co-creation activities carried out by the partners go well beyond the scope of a conventional research project. The rest of the consortium includes CoreHW, VLSI Solution, Siru Innovations, TTTEch Flexibilis, Procemex, Wapice and Cargotec.

“The SoC has been developed using the same methods that are used in industrial production, such as design for testability, extensive verification and focusing on system-level integration instead of single modules,” said Ari Kulmala, professor of practice in SoC design at Tampere University.

According to Kulmala, the chip can also be tested by external stakeholders as it includes a development kit, and it can be integrated into a wide range of other systems.

One of the key goals of the SoC Hub project is to enable rapid prototyping for new ideas, for example, in the Internet of things (IoT), machine learning and 5G and 6G technologies in silicon.

“It has been a pleasure to work with the SoC Hub team. They have been extremely quick to develop the chip, and the quality of the work has been top class,” said Bas Dorren, Director of Business Development at imec.IC-link, part of the Belgian R&D group.

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“A great deal of work has been done to enable seamless collaboration between the University and company partners. Several early career researchers have participated in designing Ballast and have therefore had the opportunity to apply the knowledge they acquired from their studies in an industrial project,” said Timo Hämäläinen, head of the Computing Sciences Unit at Tampere University.

Besides the development of the SoC, the first phase of the project was also a major undertaking, involving building the consortium and the preparation of the necessary software and licence agreements.  In the project funded by Business Finland, three SoCs will be taped out by the end of 2023. Use cases for the chips will be planned together with the project consortium.

“In the next phases of the project, we will be able to focus even more on the systematics, automation and performance of the SoCs. Despite having achieved our first goal, we continue moving forward right away. The time to invest in SoC development is now, not tomorrow,” said Hämäläinen.

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