First 22nm FGPA with hardened RISC-V cores

First 22nm FGPA with hardened RISC-V cores

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By Nick Flaherty

Gowin Semiconductor has hardened a RISC-V core and peripherals and embedded them into its latest 22nm FPGA.

The GW5AST-138 FPGA uses the A25 RISC-V CPU IP and AE350 peripheral subsystem from Andes Technology for its first complete RISC-V FPGA.

In the same way as hardened ARM cores were added to previous Gowin FPGAs, the A25 and peripherals, including a SERDES interface, avoid consuming any FPGA resources. This allows a hardware team to populate the FPGA with a design while the software team can concurrently create application code based on the RISC-V ecosystem.

The A25 hard core runs at 400MHz and supports the RISC-V P-extension DSP/SIMD ISA (draft), single- and double-precision floating point and bit-manipulation instructions, and MMU for Linux based applications.

The AE350 AXI/AHB-based subsystem comes with level-one memories, interrupt controller, debug module, AXI and AHB Bus Matrix Controller, AXI-to-AHB Bridge and a collection of fundamental AHB/APB bus IP components pre-integrated together as a system design.

A DDR3 controller and SPI-Flash controller in the FPGA fabric back up the A25’s 32KByte I-Cache and D-Cache after cache misses and off chip DDR3 provides data memory. An SPI-Flash contains the A25’s instruction memory with the code copied from SPI-Flash into DDR3 and cache upon boot-up). 

Alongside the hard instantiated IP, the GW5AST-138 FPGA fabric provides 138K LUTs for custom design implementation and Gowin provides an FPGA hardware development environment for the Arora V.  The environment supports multiple RTL-based programming languages, synthesis, placement and routing, bitstream generation and download, power analysis and in-device logic analyzer.

However this is not the first FPGA with hardened RISC-V cores. Microchip has a PolarFire FPGA with four RISC-V cores for processing and two for housekeeping, which has been used in a system on module (SoM) from Aries Embedded in Germany. 

“Andes is committed to delivering cutting-edge RISC-V technologies allowing developers to create innovative and efficient solutions. The integration of the A25 RISC-V CPU and AE350 peripheral subsystem as a hard core in GOWIN Semiconductor’s GW5AST-138 FPGA marks a significant milestone in achieving this vision,” said Andes North America VP of Sales, Vivien Lin.  “This represents a significant milestone for the RISC-V architecture as it provides our joint customers a versatile hardware development platform to create, debug, and verify their ultimate SoC design before committing their netlist for silicon fabrication. For customers not requiring an SoC, it will enable a complete RISC-V computer ready to drive their end applications.”

“In the Arora V family, we incorporate the peripherals that a RISC-V CPU typically requires in hard instantiations,” says Jim Gao, Sr. Director of Solution Development at Gowin. “We included a fully controllable high-speed SerDes for communication, video aggregation, and AI computing acceleration applications that demand very high data rates. Other instantiated functions include Block RAM modules supporting ECC error correction, high-performance multiple voltage GPIO, and high accuracy clock architecture. These hard functions save the FPGA programmable fabric of up 138K LUT’s for the designers’ unique logic implementation.”

The GW5AST-138 FPGA with SDK with GOWIN_V1.9.9 Beta-3 is available now through distribution.;



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