First 3.5D face-to-face packaging for AI processors
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Broadcom has combined 3D silicon stacking and 2.5D face-to-face packaging technology for AI processors for the first time.
The 3.5D eXtreme Dimension System in Package (XDSiP) technology integrates more than 6000 mm2 of silicon and up to 12 high bandwidth memory (HBM) stacks in one packaged device to enable high-efficiency, low-power AI computing.
The immense computational power required for training generative AI models relies on massive clusters of 100,000 growing to 1 million XPU devices that combine processor and AI accelerators. These XPUs demand increasingly sophisticated integration of compute, memory, and I/O capabilities to achieve the necessary performance while minimizing power consumption and cost.
Broadcom has more than five of these 3.5D products in development for customers with production shipments starting February 2026.
Over the past decade, 2.5D integration, which involves integrating multiple chiplets up to 2500 mm2 of silicon and HBM modules up to 8 HBMs on an interposer, has proven valuable for XPU development. However, as more complex LLMs with billions of parameters are introduced, their training necessitates 3D silicon stacking for better size, power, and cost.
The F2F packaging achieves a 7x increase in signal density between stacked dies compared to today’s face-to-back (F2B) technology along with a 10x reduction in power consumption in die-to-die interfaces by utilizing 3D HCB instead of planar die-to-die PHYs.
Broadcom’s lead F2F 3.5D XPU integrates four compute dies, one I/O die, and six HBM modules using TSMC’s 2.5D CoWoS packaging technologies. Broadcom’s proprietary design flow and automation methodology, built upon industry-standard tools, has ensured first-pass success despite the complexity of the device.
The 3.5D XDSiP has demonstrated complete functionality and exceptional performance across critical IP blocks, including high-speed SerDes, HBM memory interfaces, and die-to-die interconnects. This accomplishment underscores Broadcom’s expertise in designing and testing complex 3.5D integrated circuits.
“Advanced packaging is critical for next generation XPU clusters as we hit the limits of Moore’s Law. In close collaboration with our customers, we have created a 3.5D XDSiP platform on top of the technology and tools from TSMC and EDA partners,” said Frank Ostojic, Senior Vice President and General Manager, ASIC Products Division, Broadcom. “By stacking chip components vertically, Broadcom’s 3.5D platform enables chip designers to pair the right fabrication processes for each component while shrinking the interposer and package size, leading to significant improvements in performance, efficiency, and cost.”
“TSMC and Broadcom have collaborated closely over the past several years to bring together TSMC’s most advanced logic processes and 3D chip stacking technologies with Broadcom’s design expertise,” said Dr. Kevin Zhang, Senior Vice President of Business Development & Global Sales and Deputy Co-COO, Taiwan Semiconductor Manufacturing Company. “We look forward to productizing this platform to unleash AI innovations and enable future growth.”
“With over a decade-long partnership, Fujitsu and Broadcom have successfully brought multiple generations of high-performance computing ASICs to the market,” said Naoki Shinjo, SVP and Head of Advanced Technology Development, Fujitsu. “Broadcom’s latest 3.5D platform enables Fujitsu’s next-generation 2-nanometer Arm-based processor, FUJITSU-MONAKA, to achieve high performance, low power consumption and lower cost.”
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