First 3nm UCIe chiplet IP on TSMC CoWoS Packaging
Alphawave Semi has developed 3nm chiplet IP for the UCIe standard that is the first for TSMC’s CoWoS packaging technology
The multi-protocol subsystem IP developed by Alphawave provides 8 Tbit/s/mm bandwidth density for die to die connections with data rate of 24 Gbit/s for hyperscaler, HPC and AI devices built at TSMC.
Alphawave has implemented the PHY and controller IP in 3nm silicon optimized for the TSMC Chip-on-Wafer-on-Substrate (CoWoS) 2.5D chiplet packaging technology which uses a silicon interposer. Alphawave says this is the first time this has been achieved.
The PNY supports streaming protocols as well as the PCIe and CXL standards that are part of UCIe, and AXI-4, AXI-S, CXS, and CHI system on chip bus specifications to provide interoperability across the chiplet ecosystem. It also integrates live per-lane health monitoring for enhanced robustness and enables operation at 24 Gbps to give the high bandwidth required for D2D connectivity.
“Achieving successful silicon bring-up of 3nm 24 Gbps UCIe subsystem with TSMC’s advanced packaging is a significant milestone for Alphawave Semi and underscores the company’s expertise in utilizing the TSMC 3DFabric™ ecosystem to deliver top-tier connectivity solutions,” said Mohit Gupta, Alphawave Semi’s SVP and GM, Custom Silicon and IP.
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Alphawave Semi’s UCIe subsystem IP complies with the latest UCIe Specification Rev 1.1 and includes comprehensive testability and debug features with JTAG, BIST, DFT, and Known Good Die (KGD) capabilities.
This launch follows the first 3nm silicon with standard packaging from Alphawave in February and the release of the industry’s first multi-protocol chiplet in June. This follows the acquisition of OPenFive for its chiplet design and development expertise.
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