First CAN FD plug-fest shows interoperability
The FPGAs implementing the CAN FD data link layer – as submitted for international standardisation – were tested using different network topologies and transmission speeds. All nodes used a 40-MHz clock frequency, an arbitration bit-rate of 500 kbit/sec sampled at 80% and a data-phase bit-rate of 4 Mbit/sec sampled at 60%. The tests were performed with different busloads up to 100%. The three nodes communicated in bus-line (9 m) and passive star topologies (2 x 3 m and 1 x 6 m). The passive star was terminated with 60 Ohms at the centre point. The trace shows arbitration and data-phase oscillations with harmonics, in that configuration.
The CiA working group specifying CAN FD device and system design recommendations proposes a ration of 1:8 for arbitration/data-phase speed. In addition, the group will recommend bit-timings for different topologies as well as configuration registers for the CAN FD protocol controllers. CAN FD implementations should be clocked by 80, 40, or 20 MHz in order to minimize timing problems.
The next CAN FD plug-fest will take place in September, and anyone interested in participation may contact CiA office at www.can-cia.org CiA plans to set up a permanent CAN FD test environment for interoperability tests.
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