First IP interoperability with Intel PCIe6.0 test chip
Synopsys is demonstrating end-to-end 64 GT/s interoperability between its IP for PCI Express (PCIe) 6.0 and Intel’s PCIe6.0 test chip, an industry first.
The validation is key for integrating the IP into PCIe6.0 devices, reducing design risk and accelerating time-to-market. Several other companies including Cadence Design Systems (which will also incorporate Rambus IP) and Alphawave have shown PCIe6.0 and Marvell has also shown a test chip on a 3nm process.
The interoperability is an important step in the development of the ecosystem as PCIe6.0 adds a number of new features. Sysnopsys says it has over 24 design wins so far for the technology.
The PAM-4 electrical signaling modulation scheme introduced in PCIe6.0 produces three eyes, a shift from traditional non-return to zero (NRZ) signaling. Precoding and forward error correction (FEC) will reduce errors for analog and digital, respectively. This delivers 64GT/s bandwidth with low latency.
The new flow control unit (FLIT) packet delivery is required for the FEC, while a new L0p low-power state allows some lanes to go into a sleep mode as bandwidth requirements decrease in the system. This gives you the ability to optimize your power consumption while never shutting down the link.
The specification also uses data object exchange (DOE) as the PCIe security building block at lower bandwidth levels with cryptographic data and keys. Component Measurement Authentication (CMA) provides a firmware cryptographic signature. Integrity and Data Encryption (IDE) provides packet-level security to prevent physical attacks and coupling IDE with a controller ensures security at the 64GT/s speeds.
The IP for PCIe6.0 includes controllers, PHYs, verification IP and integrity and data encryption (IDE) security IP to accelerate development of chips for high-performance computing and AI applications.
“Our decades-long collaboration with Intel has empowered designers to implement the latest industry standards using trusted Synopsys IP,” said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. “The successful interoperability with Intel, combined with more than two dozen PCIe6.0 design wins, validates the robustness of the silicon-proven Synopsys IP for PCIe6.0 and enables designers to reduce integration risk, meet stringent requirements, and accelerate their time to market.”
“To meet the demands of data-intensive operations in the cloud and on the edge, designers require advanced connectivity and processing technologies that operate with low latency at fast speeds,” said Debendra Das Sharma, Senior Fellow and co-GM of Memory and I/O Technologies at Intel.
“Intel’s close collaboration with Synopsys, a leading PCIe IP provider, has once again resulted in successful interoperability using the latest PCIe standard. Our intent with this demonstration is to give the ecosystem confidence that Intel’s future generation products with PCIe6.0 will be interoperable with the ecosystem, enabling broad adoption of the PCIe6.0 standard.”