First Look at Samsung’s 48L 3D V-NAND Flash

First Look at Samsung’s 48L 3D V-NAND Flash

By Julien Happich

Samsung had announced its 256 Gb 3-bit multi-level cell K9AFGY8S0M 3D V-NAND as early as August 2015, stating that it would be used in a variety of solid state drives (SSD), and would be on the market in early 2016. True to their word, we managed to find them in their 2 TB capacity, mSATA, T3 portable SSD shown in Figure 1.

Figure 1: Samsung T3 2TB SSD
(Source: TechInsights)

Tearing open the drive, we find a double-sided circuit board containing four 0.5 TB capacity K9DUB8S7M packages that are shown in Figure 2. Each of these packages contain 16 of the 48L V-NAND dies that we were looking for.

Figure 2: Front and Back Circuit Board of
Samsung T3 2TB SSD (Source: TechInsights)

Figure 3 is a package cross section showing the 16 dies stacked one on top of the other and connected using conventional wire bonding technology. The dies are an outstandingly 40 µm thin, perhaps the thinnest dies that we have seen in a package. By comparison, the dies in Samsung’s 32L V-NAND that we examined in 2014 were about 110 µm thick and stacked 4 dies high in their package.

Other thin memory dies that we have seen include Hynix’s HBM1 memories used in AMD’s R9 Fury X graphics cards that are about 50 µm thick, and some 55 µm thick DRAM dies in Samsung’s DDR4 with 4 stacked dies with TSV interconnections.

So 40 µm is really thin and might be close to the thinnest that can be achieved with 300 mm diameter wafers without a carrier wafer. We are impressed!


Figure 3: 16 Stacked Samsung 48L V-NAND Dies (Source: TechInsights)

One of the 256 Gb dies is shown in Figure 4 and comprises two 5.9 mm x 5.9 mm large banks of NAND Flash memory. We can calculate a gross measure of the memory density by dividing the entire die area into the memory size to get about 2,600 Mb/mm2. By comparison, Samsung’s 16 nm node planar NAND flash measures about 740 Mb/mm2. So while the V-NAND is fabricated at a larger process node (~21 nm vs. 16 nm), its memory density is almost 3.5 times better than the 16 nm planar NAND flash (see Table 1).

Table 1: Planar and V-NAND Density

We have just begun our analysis of the 48L V-NAND, and Figure 5 is a SEM cross-section taken through the array portion of the memory. We see 55 gate layers in the stack: 48 NAND cell layers, 4 dummy gates, 2 SSL and 1 GSL. Two V-NAND strings, each having a polysilicon annulus surrounded by a charge trap layer and metal gates, are visible between the tall tungsten filled sourceline contacts.

Figure 4: Samsung K9AFGD8U0M 256 Gb
V-NAND die (Source: TechInsights)


Figure 5: SEM Cross Section 48L V-NAND
Array (Source: TechInsights)

Figure 6 is a higher magnification image of the top portion of the V-NAND string. The top surface of the polysilicon annulus (NAND string channel) is contacted by a tungsten bitline strap that connects to the overlying bitlines. The metal word lines, oxide barrier and charge trap layers surround the polysilicon channel layer.

We can’t yet show you the fine structure of the 48L V-NAND array, as it just went into our labs, but we can show some features that we found in Samsung’s 32L V-NAND in Figure 7. The polysilicon annulus that forms the NAND string channel contacts the selective epitaxially grown (SEG) contact that protrudes upwards from the substrate. A metal gate lying over top the substrate serves as a select gate for the adjacent sourceline.

Figure 6: Upper Portion of V-NAND Array (Source: TechInsights)

The polysilicon channel layer is surrounded by a thin tunnel dielectric that is likely formed by atomic layer deposition (ALD). A charge trap layer, typically silicon nitride, is in contact with this tunnel dielectric and covered by an oxide barrier layer. These were also likely formed by ALD. A barrier layer oxide and metal gate (word lines) surround the charge trap layer.

Charge trap layers are a fairly new design for Flash memories, as they typically use polysilicon floating gates to store charge. We have seen silicon nitride trap layers being used by Spansion in their MirrirBit NOR Flash memory, but Samsung might be the first to use the charge trap layer in NAND Flash. Figure 8 shows the NAND string in plan view, confirming the annular shape to the layers.

Figure 7: TEM Cross Section Samsung
32L V-NAND (Source: TechInsights)


Figure 8: TEM Plan View of V-NAND
String (Source: TechInsights)

Up until recently, we have only seen Samsung’s V-NAND in the form of stand-alone SSDs and we began to wonder how long it would be before they would show up in consumer products. Our wait was not long as Microsoft has included 128 GB V-NAND based SSDs in their Surface Book and Surface Pro 4 laptops that our division tore down in January of this year.

We have also been looking for them in smartphones, and we thought had found them in the universal flash storage (UFS) NAND Flash memory used in Samsung’s Galaxy S7 (Figure 9). This 32 GB UFS 2.0 memory is claimed to have a lower power consumption and smaller form factor than its predecessor: the eMMC type memory module. And we were hopeful that it might contain some 32L V-NAND, but this was not to be, as we found their 16 nm planar NAND flash instead (Figure 10).

Figure 9: Samsung 32 GB
UFS 2.0 (Source: TechInsights)


Figure 10: Samsung 16 nm planar NAND Flash
Array (Source: TechInsights)

Our search for V-NAND in smartphone continues. And we expect Samsung to be the first to introduce them as they were first to market with their 32L V-NAND in 2014 and first to market with 48L in 2016. With V-NAND fabs running in both South Korea and Xi’an China, we think Samsung has deeply committed to V-NAND, and the end of planar NAND scaling is at hand.


About the author:

Kevin Gibb is Product Line Manager at TechInsights –  

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