First MPEG-5 video compression IP
Allegro DVT has launched the first IP for the new MPEG-5 Low Complexity Enhancement Video Coding (LCEVC) decoder standard.
The D301 block is expected to accelerate the adoption of the new video standard by allowing SoC/ASIC vendors to enhance existing H.264/HEVC/AV1/VVC designs for lower power and additional features.
The MPEG-5 part 2 LCEVC standard specifies an enhancement layer that can be which, when combined with a base video encoded with a separate codec such as H.264 or H265/HEVC/VVC, produces an enhanced video stream. The enhanced stream provides new features such as extending the compression capability of the base codec, lowering encoding and decoding power consumption, and providing a platform for additional future enhancements.
- First hardware VVC/H.266 video decoder IP core
- H.265 video encoder supports 4K and HD resolutions
- Open source H.265 video codec for NXP’s iMX 8M
The D301 LCEVC decoder IP is optimized for power and silicon area, making it suitable for system-on-chip (SoC) designers to easily integrate LCEVC decoding into their products. It supports picture resolution up to 8K, pixel widths from 8 to 12-bits and chroma subsampling formats ranging from 4:2:0 up to 4:4:4. The IP also has full user configurable control software.
“We are very excited about Allegro DVT’s introduction of their LCEVC decoder IP. Allegro DVT’s product launch represents a cornerstone towards delivering the first HW enabled LCEVC decoding solutions which are key to optimizing power consumption and to supporting higher resolutions,” said Guido Meardi, CEO of V-Nova, the London-based IP and software company that developed a highly optimized library for LCEVC.
“We are proud to be the first company to offer an LCEVC decoder IP solution. Our D301 will enable our customers to integrate the new standard into their products quickly and easily, providing them with a significant competitive advantage,” said Nouar Hamze, CEO of Allegro DVT.
www.lcevc.org/; www.v-nova.com/; www.allegrodvt.com
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