First multithreaded DSP core targets OpenRAN
Ceva in Israel has launched a dual threaded vector processing block that scales up to eight threads for next generation 5G Advanced OpenRAN infrastructure and terminal designs.
The first member of the fifth generation architecture, the CEVA-XC22, supports two threads with a Dynamic Vector Threading (DVT) scheme, which supports true hardware multi-threading. This was previously only found in general purpose CPU architectures.
DVT enables optimal sharing of vector resources between different execution units, resulting in higher vector processing efficiency. This boosts the overall efficiency of common 5G execution kernels, boosting the overall power efficiency.
The core, launched at Mobile World Congress 2023 (MWC) in Barcelon next week, is designed to address next-generation 5G-Advanced workloads across a broad spectrum of use cases, including smartphones, high-end Enhanced Mobile Broadband (eMBB) devices such as Fixed Wireless Access and Industrial Terminals and a range of cellular infrastructure devices such as base stations, virtualized DU accelerators, and beamforming compute in Massive MIMO radios.
The architecture was designed in consultation with CEVA’s leading Tier 1 OEM customers, with the common aim of improving mobile network performance and power efficiency.
It will scale to four and eight threads (expected to be called the CX24 and XC28 cores) by instantiating the XC22 cores, each with the Vector Compute Unit, DVT and dual processing elements and the independent program and data memory blocks. These share the global cache and the allocation of threads is controlled by the compiler.
“5G-Advanced and beyond promise ever-increasing cellular bandwidth and lower latency, while being greener and more energy efficient. This creates significant challenges for wireless device companies and mobile network operators who need to deliver on this promise,” said Guy Keshet, Vice President and General Manager of the Mobile Broadband Business Unit at Ceva.
“Our CEVA-XC20 DSP architecture addresses these challenges, leveraging more than 30 years of expertise in cellular DSPs at CEVA to deliver incredible power efficiency for the most intense baseband compute use cases. We’re proud to work together with our customers to constantly improve the cellular user experience while reducing the environmental impact of new technology.”
The CEVA-XC22 will also be integrated within Ceva’s baseband platforms, PentaG-RAN for cellular infrastructure and PentaG2-Max for high performance mobile devices alongside dedicated accelerator blocks.
The CEVA-XC22 DSP will be available for general licensing in the second quarter of this year. CEVA-XC22 customers can also benefit from ASIC/SoC co-creation services by Ceva’s Intrinsix team to help integrate and support system design and modem development.
www.ceva-dsp.com/product/ceva-xc22/
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