First open-source SystemVerilog RISC-V processor functional coverage library
Imperas Software in the UK has developed the first open source SystemVerilog RISC-V processor functional coverage library for RISC-V cores.
The initial release is for RV32IMC, RV64 and other ratified extensions are under development and will also be released as part of the riscvOVPsimPlus package with a free-to-use permissive license. This covers free commercial as well as academic use.
Imperas is a leading developer of verification tools for the RISC-V open instruction set architecture and had previously developed these libraries over time to support multiple customer projects and users. It was also involved in the IoT development kit launched at Embedded World in June.
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The development of an instruction level SystemVerilog functional coverage library requires both an understanding of the verification process and the general requirements of the DV community.
SystemVerilog was adopted as a standard by IEEE and Accellera based on Superlog originally developed by Co-Design Automation which included Imperas founder and CEO Simon Davidmann, Peter Flake, and Phil Moorby. The history and development of SystemVerilog was the subject of a paper at the ACM (Association for Computing Machinery) prestigious HOPL IV event in 2021 which is held every 10 years.
The full text of the paper, ‘Verilog HDL and Its Ancestors and Descendants’, is available at https://dl.acm.org/doi/10.1145/3386337
“Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture,” said Allen Baum of Esperanto Technologies, Inc., and Chair of the RISC-V International Architecture Test SIG. “The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.”
“The open standard ISA of RISC-V provides great flexibility for innovation in the design of modern processor implementations,” said Simon Davidmann, CEO at Imperas. “With all the configurability offered by the standard extensions and implementation options, plus users-defined custom features, the total scope of the RISC-V verification effort cannot be understated. Through our experience working with some of the most sophisticated customer designs we recognize the usefulness of ready-to-use SystemVerilog Verification IP that allows developers a solid foundation on which to build a successful DV plan.”
The riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, latest test suites and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.
ImperasDV is available now, more details are available at Imperas.com/ImperasDV.
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