First PCIe 6.0 and chiplet test chip on 3nm
Marvell Technology has shown a test chip for the latest PCIexpress 6.0 high speed interconnect standard, built on 3nm process technology.
PCIe is the key protocol for the CXL 3.0 specification for data centre chips, and the 3nm test chip built by TSMC also includes building blocks for 112G XSR SerDes (serializer/de-serializer), Long Reach SerDes and a 240 Tbit/s parallel die-to-die interconnect for chiplets.
These technologies also support all semiconductor packaging options from standard and low-cost RDL (Redistribution Layers) to silicon-based high-density interconnect.
Marvell was the first data infrastructure silicon supplier to sample and commercially release the 112G SerDes technology and has been a leader in data infrastructure products based on TSMC’s 5nm process. The chips with these test blocks highlight the move to the next generation of process technology that is just entering volume production.
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SerDes and parallel interconnects serve as high-speed pathways for exchanging data between chips or silicon components inside chiplets. Together with 2.5D and 3D packaging, these technologies can reduce system-level bottlenecks. SerDes also help reduce pins, traces and circuit board space to reduce cost. A rack in a hyperscale data centre might contain tens of thousands of SerDes links.
The parallel die-to-die interconnect, for example, enables aggregate data transfers up to 240 Tbit/s 45% faster than available alternatives for multichip packaging applications.
Marvell incorporates its SerDes and interconnect technologies into its flagship silicon solutions including Teralynx switches, PAM4 and coherent DSPs, Alaska Ethernet physical layer (PHY) devices, OCTEON processors, Bravera storage controllers, Brightlane automotive Ethernet chipsets and custom ASICs. Moving to a 3nm process enables lower cost and power consumption while maintaining signal integrity and performance.
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“Interconnects are taking on heightened importance as clouds and other computing systems grow in size, complexity and capability. Our advanced SerDes and parallel interfaces will play a significant role in providing a platform for developing chips with best-in-class bandwidth, latency, bit error rate, and power efficiency for meeting the demands of AI and other complex workloads,” said Raghib Hussain, president of products and technologies at Marvell.
