First PCIe 6.0 clock buffers and multiplexers
Renesas Electronics has introduced the first clock buffers and multiplexers that meet the requirements of the PCI Express 6 (PCIe 6.0) specifications.
There are 11 new clock buffers and four new multiplexers that also support and provide extra margin for PCIe Gen5 implementations. These complement Renesas’ low-jitter 9SQ440, 9FGV1002 and 9FGV1006 clock generators to provide a complete PCIe Gen6 timing design for data centre/cloud computing, networking and high-speed industrial applications.
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The PCIe 6.0 standard supports higher data rates of 64 GTransactions/s while requiring very low clock jitter performance of less than 100fs RMS. The RC190xx clock buffers and RC192xx multiplexers have PCIe Gen6 additive jitter specs of only 4fs RMS, future-proofing customer designs for the next generation of industry standards. The devices also have 1.4ns in-out delay, 35ps out-out skew, and -80dB Power Supply Rejection Ratio (PSRR) @100kHz for easier system design.
The devices have selectable SMBus addresses to allow easy use of multiple devices with SMBus write-protect to boost system security. A Loss-Of-Signal (LOS) output supports system monitoring and redundancy while a 4-wire Side-Band interface supports high-speed serial output enable/disable and device daisy-chaining. Power Down Tolerant (PDT) and Flexible Start-up Sequencing (FSS) features ensure good behaviour under abnormal system conditions.
“PCIe Gen6 timing will be at the heart of new equipment in data centres, high-speed networking and other applications,” said Zaher Baidas, Vice President of the Timing Products Division at Renesas. “As we have done for preceding generations, Renesas is providing customers with the first timing solution to enable these new, higher-performance systems. Our customers know that we have the technical expertise and market knowledge to ensure that their products will be able to meet future requirements as well.”
“By delivering the first discrete timing solution for PCIe Gen6, Renesas is enabling customers to develop the next-generation of high-performance systems,” said Rich Wawrzyniak, Principal Analyst for Semico Research. “It will be interesting to see the innovative implementations that result from this new capability, especially when considering how solutions for the emerging Chiplet market are starting to evolve, with the need for increasing speed and bandwidth as an underlying constant.”
Renesas has combined the RC190xx clock buffers and RC192xx multiplexers with other analog and power devices for a full power and timing reference design for Intel’s latest generation Xeon CPU platform. The pre-tested design includes the Renesas 9SQ440 clock generator, multiple smart power stage devices, an LDO, a USB host controller, and a DDR5 server PMIC at renesas.com/win.
Renesas also offers a complimentary Clock Tree Design Service where in-house experts assist customers in building a new clock tree from the ground up or evaluating and improving an existing clock tree design.
The RC190xx buffers are offered in 4-, 8-, 13-, 16-, 20- and 24-output configurations. The RC192xx multiplexers include 2-, 4-, 8- and 16-output versions. The new devices are offered in packages as small as 3mm x 3mm. All of the new devices are available now, along with an evaluation board schematic.
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