First single chip quad 10G Ethernet transceiver
The flexible physical layer PHY in the TLK10034 serializer/deserializer (SerDes) allows engineers to use one SerDes for all of their protocols instead of stocking multiple devices. The TLK10034 interfaces to backplanes, copper cables, and SFP+ optical modules in server, storage and enterprise networking equipment.
The TLK10034 provides multiple protocol flexibility as each of the four bi-directional channels supports 10GBASE-KR, XAUI, 1GBASE-KX, CPRI, and OBSAI standard protocols, providing engineers with maximum flexibility in their system designs. It also enables optimized link performance through link training to seamlessly brings up the link, and optimizes the transmitter pre-emphasis levels to minimize system bit error rate (BER). It consumes 825 mW (typical) per channel, compared to competitive SerDes that consume more than 1 W and forward error correction (FEC) manages the signal integrity performance by compensating up to 29-dB insertion loss at 6 GHz to improve BER and system margin.
System designers can create a robust data link by combining the TLK10034 with the LMK04906 clock jitter cleaner/multiplier.
The TLK10034EVM evaluation module (EVM) can be purchased today for US$2999, and the TLK10034SMAEVM SMA breakout daughterboard can be purchased for US$1499 to evaluate low-speed signals. A GUI software tool for the TLK10034EVM can be downloaded to manage device provisioning and testing, and HSPICE and IBIS-AMI models are available to verify the TLK10034’s signal integrity.
The TLK10034 is available today in a 19-mm by 19-mm, 324-pin PBGA package for a suggested retail price of US$45 in 1,000-unit quantities.