Flash, STT-MRAM and resistive RAM: they all come with different challenges
At imec, we mostly focus on three concepts which all come with different challenges.
First is Flash, and specifically 3D NAND. Here it’s the integration challenge that is keeping us all busy. Before, the focus was on device scaling, but now it’s all about stacking more layers. Last year, we explored new materials for the channel (e.g. III-V channel in 3D NAND) and for the trapping layer (YAlO instead of SiN), in parallel with device reliability characterization and modelling.
Another important memory type is STT-MRAM where a complex magnetic stack makes the scene. Focus here is on choosing the right material combination and developing the perfect stack (with perfect interfaces!). Over the last years, imec made a lot of progress to build a good stack. But even more challenging is the patterning of this multi-layers structure without affecting the magnetic properties of the device.
Very recently we were able to demonstrate 45nm devices with good performance. Tool suppliers are improving the etch platforms and I expect STT-MRAM as embedded memory in the foundries by 2017 and as standalone memory by 2020. In the latter case, more scaling is necessary and this implies more etch issues which will have to be solved.
Thirdly, we explore resistive RAM. The challenge for this type of memory is picking the right combination out of the numerous kinds of stacks and materials. And to do this, you need a fundamental understanding of what happens inside each stack. Imec has developed in depth characterization and modelling on OxRAM and CBRAM memories, expected to be used in embedded applications.
Globally, RRAM suffers from a trade-off between write energy and stability. VMCO is another RRAM variant developed at imec to break this trade-off. To be competitive in standalone applications, RRAM will also need to be combined with a selector, which requires again material selection and benchmarking. This is a role that imec is willing to take on for its partners.
Finally, there is also a high-level challenge that the memory researchers and developers are facing. It’s the changing landscape in which emerging memories have more and more impact on the system architecture.
Before, the system hierarchy was built with the memory technologies that were available. In the future it might be the other way around: the system architects will tell us what to develop. A closer collaboration between the device team and system architects is therefore indispensable. Imec’s memory ‘insite’ activity will tackle this challenge.
About the author:
Arnaud Furnemont is memory department director, MRAM and Flash program director at imec – www.imec.be
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
