Flexible fab could slash chip shortage
Silicon isn’t everything, says Richard Price at PragmatIC, a startup in Cambridge, UK specialising in flexible plastic chip technology.
A recent finalist in the technology awards for the Royal Academy of Engineering, the company has developed a chip-making process it calls FlexLogIC that has a dramatically shorter design and production time, especially for chips on older process technologies. This can fundamentally change the way chips are designed, especially for low cost sensors in the Internet of Things (IoT) says Price.
“There is an intersection in the low end complexity and IoT and RFID where there isn’t a great deal of value in the conventional semiconductor production on older lines,” he said.
“We have a 0.8um technology and a roadmap to shrink that, certainly down to 300nm and we have R&D for that. It’s an NMOS technology which means it has some limitations in scalability, the noise margins and power. We have been working on CMOS and we expect to bring this into production over the next few years,” said Price.
“We are very comfortable with thousands of gates, and conceptually we can go 100 times more complex. A few thousand gates is a few square mm, and we have proven denser circuits. There’s quite a lot of process and design optimisation that can shrink that further.”
This is linked to the manufacturing process, which is based on a flexible substrate rather than silicon. The process technology can be set up quickly and relatively cheaply locally around the world.
“FlexLogic is our fab in a box and deploying these locally around the world to meet demand as a distributed megafab. We have a beta PDK [process design kit] with a formal release and we are working with a range of industry and academic design partners. Some are looking at proprietary RFID but we are working with ARM on designs,” said Price.
“The mini fabs can be built in 12 month process, but we know we can get that below 6 months ad as we start to do those simultaneous it can be under 4 months to add extra capacity. It’s a combination of our technology and working with our global partners as equipment providers,” he said. “We are planning our second installation in the UK which will be the blueprint for rolling this out and within the next two years we will be bringing online additional capacity outside the UK.”
Each of the distributed fabs can produce billions of flexICs per year each costing between one cent and ten cents.
“It’s a combination of product design and pushing the boundaries of the technology,” he said. “With ARM we published a paper in Nature Electronic that was a hardware optimisation of a machine learning engine for a sensor. This came out of an InnovateUK with the University of Manchester and Unilever looking at ways to produce a low cost sensors for volatile organic compounds, smells or signatures from food or other types of decay or even disease. There are implementations that make sense without CMOS,” he said.
This also changes the design process as a custom version of a chip can be designed and produce din just a few weeks, rather than months or years.
“One of the features of the technology is because the cost is low and the design cycle is short we can do multiple design iterations to get an optimised solutions so a general purpose controller may not make sense and that was the approach with the odour sensor with ARM. It allows you to strip out the complexity from the circuit,” he said.
“We are talking a week for the design cycle and manufacturing is days, and in many cases the applications are looking at large volumes of 10m or 100m devices, so the dynamics you see in silicon design are not the same for us,” he said. “There is a place for low complexity general purpose designs but a lot of what we see is hardware optimised for particular applications.”
The process can even integrate the passives from a PCB onto the chip, which helps boost recycling rates and reduce e-waste. “We can implement capacitors and resistors in the process as well,” he said.
Next: Plans for packaging
The polyimide substrate potentially brings issues with conventional production lines, but the company has used the technology for a range of RFID chips that have given it insights into the packaging requirements.
“We have been working on different assembly and packaging solutions driven by chip assembly for RFID using anisotropic conductive paste but also with wire bonding and low temperature soldering,” said Price. “The indications are that we are compatible with industry standard processes with some modifications – essentially the chip is self packaged. You can handle it with pick and place and the substrate itself is an engineered polymer so its not an issue for its to go through reflow for PCB assembly,” he said.
“We are also looking at more sustainable approaches including compatibility with substrates for paper, copper on paper and we see opportunities to aluminium which will be interesting,” he said.
The size of die is tens of square mm up to 50 sq mm, beyond that is possible but the company haven’t fully characterised that yet, he says. The power rail is typically in the 2.5 to 3V range, although it depends on the complexity, power and the design
“We operate at 13.6MHz for RFID but in a lot of applications operate in the kHz range and that means we can reduce the power. We are also working on a Schottky device which allows us to increase the speed to hundreds of MHz or GHz but that’s not necessarily for all designs. For energy harvesting and rectification we can do that at higher frequencies, and that would focus on RF as the power source,” he said.
Complexity
The company is looking at more complex system on chip devices using the process, but Price questions whether this is a symptom of the linking that leads to the chip shortage.
“An ARM core is possible, and for us it would be a trade off of complexity and cost up to a certain level and that crossover point will move further to our benefit, At the moment we are researching more complex with tens of thousands of gates. With a 50,000 gate general purpose design you could strip that back to 5000 gates for a specific applications so you can shrink the die for lower cost,” he said.
“Its definitely viable both technically and commercially but its not always going to be the right approach.”
“For example what’s interesting is moving into wearables with something that is optimised for the form factor and can be scaled up, such as a wearable ECG patch with optimised hardware to look at a particular condition with predictive monitoring,” he said. “The pitch to the designers is you can afford to fail several times to get to your optimised design. We provide this rapid route to the solution.”
The next phase of the foundry is scaling up and addressing a mix of different types of customers. “Design houses will be an important part but there’s also a opportunities in universities and research institutes with rapid tapeout and production with an undergraduate programme such as imec in Belgium,” he said.
“As a foundry we shouldn’t be proscribing what people want to do – there will be many weird and wacky ideas that we haven’t thought of and we are looking forward to that,” he said.
The RFID work was a demonstration of the technology. “Generally we see our main business as a foundry rather than a product company,” he said
Other articles on eeNews Europe
- TI buys Micron’s Utah fab for $900m
- Asian lockdown creates global MLCC capacitor shortage
- Nexperia spins out its semiconductor equipment business
- Nexperia buys Newport Wafer Fab
- Sony loses market share in image sensors
- Plans start for TSMC 2nm fab
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
