FlexTiles European project hints at reconfigurable 3D chips
Deliverables to be presented at a workshop during the 24th International Conference on Field Programmable Logic in Munich next September include an OVP-based (Open Virtual Platform) simulator and FPGA demonstrators for the heterogeneous many-core architecture that was developed by the nine project members across five countries.
The consortium also came up with a complete tool-chain for the use of the so-called FlexTiles architecture, which although proven as a concept and through hardware emulation, has yet to be integrated as a SoC.
Coordinated by aerospace and defence French giant Thalès, the project’s main goal was to develop a programmable heterogeneous many-core platform which can be reconfigured on the fly to meet advanced processing needs such as surveillance drones or driverless cars.
The efficient programming of multi-core architectures is critical for embedded systems on a tight power budget or simply to build energy-efficient supercomputers, but the challenge remained an unresolved issue despite the growing number of cores being used in embedded systems.
By 2020, many-core solutions are expected to boast in excess of a thousand processor cores, calling for truly self-adaptive programmability, a more efficient way to explore embedded system optimisation on-the-fly than what manually coded reconfiguration scenarios could offer.
The FlexTiles concept consists of a 3D stack of 2 dies forming a chiplet – see figures 1 – including on one layer a number of 2D interconnected general purpose processors (GPPs) and accelerators such as DSPs and embedded FPGAs (the many-core layer, and on a second layer, a reconfigurable embedded FPGA managed by a dedicated controller.
Fig. 1: The FlexTiles concept: a dual layer 3D chip with many cores on one layer interconnected through a reconfigurable embedded FPGA layer.
A virtualization layer on top of a kernel hides the heterogeneity and the complexity of the many-core platform from its programmer and fine-tunes the mapping of an application at runtime.
The virtualization layer provides self-adaptation capabilities by dynamic relocation of application tasks to software on the many-core layer or to hardware on the reconfigurable layer – see figure 2.
Fig. 2: The FlexTiles programming tool-flow makes it transparent for application developers to use the many-core heterogeneous architecture.
This self-adaptation is used to optimize load balancing, power consumption, hot spots and resilience to faulty modules.
“The self-adaptive capabilities of the programmable heterogeneous many-core platform defined in the FlexTiles project are key to optimise priorities at runtime”, explained Dr Philippe Millet, senior research engineer & project manager at Thalès, and coordinator of the FP7 FlexTiles project.
“With our programming methodology, application designers can decide what parameters can be used to map their application to the many cores, setting task priorities while managing power consumption, memory availability, or response latencies.” Millet added.
“At run time, the reconfiguration controller and the application always know the status of the chip, what resources are available” added Marc Morgan from the Centre Suisse d’Electronique et de Microtechnique S.A.(CSEM), involved in the project to provide his expertise on ultra low-power processors and DSP accelerators.
“Each application can ask for specific resources, these requirements will change along time, but the flexibility and priorities are set for each application”, Morgan continued.
“For example, you could have a video surveillance camera with low resource requirements in video analytics, until a trigger event calls for more processing power to follow a specific car or to track an object. The new programming methodology makes it transparent for application developers to interface with the resource manager and the virtualization manager”, Morgan concluded.
The dedicated tool-flow developed during the three years of the project’s duration is said to improve programming efficiency while reducing the impact on time to market, it is expected to reduce the development cost of many-core solutions by 20 to 50%.
In principle, the basic FlexTiles 3D SoCs assembled using TSVs (through silicon vias) could be further assembled into larger systems packages using interposers – see figure 3.
Fig. 3: The future: implementing the FlexTiles as low-cost high-volume chiplets to be flexibly assembled into larger systems using interposers.
Hence the FlexTiles SoCs could be designed as high-volume and low-cost, generic chiplets adaptable in numbers to serve a broad range of signal and image processing applications.
This will be the topic of the follow up project, FlexTiles-II for which Millet is seeking another set of partners, which could well include some established FPGA vendors.
Although this is looking far ahead, such generic purpose chiplets could well justify a spin-off company, one that could offer a European alternative to the US-based heterogeneous many-core solutions put forward by companies such as Intel with its hybrid Xeon-FPGA package announced in June (most probably involving Altera), or that put forward by IBM tying up Xilinx FPGAs with its CAPI (Coherence Attach Processor Interface) protocol.
We have yet to see if FPGA vendors would want to be involved in such chiplets, of if it would make sense at all for them to cannibalize their own high-end FPGA markets with such a versatile many-core solution.
For the time being an FPGA-based FlexTiles development platform is commercially available from project partner Sundance Multiprocessor Technology Ltd. The hardware emulator relies on two Virtex 6 Xilinx FPGAs.
More information about the FlexTiles architecture at www.flextiles.eu and www.flextiles.biz
More about the Open Virtual Platform at www.ovpworld.org
Registration for the FlexTiles workshop during FPL2014: https://flextiles.eu/WordPress3/?ai1ec_event=fpl-2014
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