The new JasperGold platform incorporates Smart Proof Technology to improve verification throughput for all JasperGold apps. Machine learning is used to select and parameterize solvers to enable faster first-time proofs. Additionally, machine learning is used to optimize successive runs for regression testing, either on premises or in the cloud. With Smart Proof Technology, proofs speed up by up to 4X, and up to 6X on regression runs.
“We measured averages of 2X faster proof performance out of the box and 5X faster regression runs across our design testcases with the new smart JasperGold platform,” stated Mirella Negro Marcigaglia, Digital Design Verification Manager at STMicroelectronics. “We are also seeing non-converged properties reduced by over 50%. Combined, these improvements significantly boost our verification productivity.”
Given today’s larger and more complex SoC designs, the design compilation process sets the maximum size of design, and the compute resources necessary, to start formal analysis. The updated JasperGold platform delivers more than 2X design compilation capacity with an average of 50% reduction in memory usage during compilation, compared with one year ago. Additionally, engineers can effectively scale design capacity through advanced parallel compilation technologies that optimally use available compute resources, and by running proofs on the Cloud.
The platform’s new formal coverage technologies let engineers perform IP signoff purely within the JasperGold platform. These new formal signoff technologies include improved proof-core accuracy, new techniques to derive meaningful coverage from deep bug hunting and new formal coverage analysis views. Together those features deliver signoff-quality formal coverage metrics and enable multi-engine chip-level verification closure.
Part of the Cadence Verification Suite, the JasperGold formal verification platform offers comprehensive coverage in the vManager metric-driven signoff platform, which combines JasperGold formal results with Xcelium simulation and Palladium emulation metrics to speed overall verification closure.
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