SilTerra has worked with partner VeriSilicon Holdings Co. Ltd. (Shanghai, China) to release the 180nm process with an accompanying physical design kit.
The process offers a thin gate CMOS with a leakage current that is 95 percent less than the generic 180nm CMOS from the company. This will make the process more suitable for applications such as smart metering, sensors, RF proximity tags, and wearable equipment.
The process comes with multiple options for threshold voltage and has a 2.97 square micron six-transistor bit cell. There are modular process option such as RFCMOS passive and active devices, as well as embedded flash memory.
VeriSilicon has releases the physical IP design kit which includes a ‘7-track’ standard cell library with memory compiler and a programmable circuit under pad I/O library.
“SilTerra has been very focused in developing technology roadmap and IPs to help our customers design critical IoT building blocks such as microcontrollers (MCU), sensors (MEMS), and Bluetooth Low Energy (BLE),” said Yit Loong Lai, executive vice president of sales and marketing of SilTerra, in a statement.
Starting commercial production in 2001, the company’s headquarters and factory are located in Malaysia’s Kulim Hi-Tech Park, with sales and marketing offices in San Jose, California and Hsinchu, Taiwan.
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