Four pilot lines for the EU chip joint undertaking

Four pilot lines for the EU chip joint undertaking

Technology News |
By Nick Flaherty

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The EU has announced four pilot lies for semiconductors, for leading edge chips below 2nm, low power FD-SOI, chiplets and wide bandgap devices.

The pilot lines from the Chips Joint Undertaking (Chips JU) will see imec in Belgium developing technologies below 2nm,  while the FD-SOI line at CEA-Leti in Grenoble, France is heading down to 7nm.  

Tampere University in Finland will host a system in package pilot line for wide bandgap devices such as silicon carbide and gallium nitride, while the Advanced Heterogeneous System Integration Pilot Line will be led by Fraunhofer in Germany. 

The pilot lines will receive grants for the set-up, integration and process development, and for operational activities and will be funded jointly by the EU, from the Horizon Europe and Digital Europe Programme, the Member States and private contributions.

A call for a virtual Design Platform is currently open.

“The selection of these pilot lines marks a pivotal moment for Europe’s semiconductor industry, showcasing the collective commitment of European states to drive technological innovation,”  said Kari Leino, Chair of the Chips JU Public Authorities Board.

“This decision represents a significant milestone for Europe’s semiconductor industry, and we look forward to the realisation of these pilot lines. Through collaboration and innovation, we aim to drive progress and excellence in Europe,” said Jari Kinaret, the Executive Director of the Chips Joint Undertaking.

“We are looking forward to Tynall National Institute participation in both the imed leading edge beyond 2nm and CEA-Leti FD-SOI pilot lines and working with all the other partners involved in support of the Irish and European semiconductor industry,” said William Scanlon, CEO of the Tyndall National Institute.

Tampere University is a partner in the WBG Pilot Line, which focuses on developing wide bandgap (WBG) semiconductors and testing and integrating WBG chips for motor control systems, battery management systems, fast charging systems, photovoltaic inverters, power supply systems and 5G base stations.

Tampere University’s budget for the MBG Pilot Line is €40m from the Finnish government and the European Commission. It aims to set up the System-in-Package Fabrication (SiPFAB) pilot line in Tampere for testing WBG chips and integrating and packaging chip systems.

“In the next few years, we will continue to expand the University’s expertise in semiconductor technology. Tampere will become a major hub of semiconductor expertise in Europe that will attract both academic professionals and new businesses,” said President of Tampere University Keijo Hämäläinen

“Hosting the pilot line was an important goal in the Chips from Tampere programme, and we are delighted that this goal was achieved so soon. The pilot line will enable us to create next-generation chip solutions for electrification, safety and data communications. The next step will be the establishment of a competence centre for building semiconductor expertise,” said Petri Räsänen, director of Business Tampere’s Chips from Tampere programme.

The pilot lines will accelerate process development, test and experimentation, and validation of design concepts. Their implementation is expected to bridge the gap from lab to fab and will be available to a wide range of users, including academia, industry and research institutions.

Following this announcement, the next steps include negotiations with the consortia to finalise the Hosting Agreements, Joint Procurement Agreements and the related Grant Agreements by the end of 2024.

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