FPGA accelerator board hosts Xilinx Kintex Ultrascale
The ADC-PCIE-8K5 features up to 32 GB of DDR4-2400 ECC memory, dual SFP+ networking I/O ports, dual 4x16G FireFly expansion I/O ports, and built in USB accessible system monitoring and JTAG debug port. The hardware is supported by the Xilinx SDAccel tool for OpenCL, and Xilinx Vivado for HDL and HLS flows. Alpha Data offers Board Support Packages (BSP) including high-performance PCIe/DMA, OpenPOWER Architecture CAPI, FPGA example designs, plug and play O/S drivers, and a mature Application Programming Interface (API). The ADC-PCIE-8K5 is IBM POWER8 compliant.
At a GPU Technology Conference in San Jose, California this week (April 5-8, 2016) a team from Pennsylvania State University and SiliconScapes will be running demos on Alpha Data FPGA boards to show real-time vision algorithms and implementations. The Microsystem Design Lab will highlight several advancements such as the NSF funded “Visual Cortex on Silicon” research expedition, led by Professor Vijay Narayanan, which forges collaboration with over eight universities and industry partners including IBM and SiliconScapes. The goal is to advance the state-of-the-art in embedded vision systems by taking a holistic approach that considers algorithms, devices and compute fabrics.
The team is focusing on creating advanced real-time vision systems that can aid a visually impaired person navigate environments with the ease and independence of a normal-sighted person. To demonstrate, a participant wears a camera enabled smart glass device. The glass offloads object detection to a CAPI enabled IBM POWER8 server to locate grocery items on a mock grocery shelf. With their eyesight obstructed, the participant is provided auditory feedback to guide them to grab an item of interest.
In addition to this interactive demo Penn State and SiliconScapes will exhibit implementations of visual object detection and classification for applications such as driver assistance, surveillance, and augmented reality. These vision algorithms are accelerated on an IBM POWER8 system utilizing custom hardware accelerators mapped to Xilinx FPGAs and Alpha-Data accelerator cards. This work is funded in part by NSF Expeditions in Computing program.
Alpha Data; www.alpha-data.com/8k5
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