FPGA-based prototyping tool improves speed and turnaround time
The algorithms in the latest Certify software release have been tweaked to produce up to 30 percent faster FPGA-to-FPGA transmission performance using High-Speed Time Domain Multiplexing (HSTDM), which results in higher overall performance of designs prototyped with Synopsys’ HAPS FPGA-based prototyping systems. Both tools now incorporate incremental compilation technology that accelerates implementation of design revisions, as well as automation to ease the partitioning of large designs into multiple HAPS boards.
"The new Certify and Identify releases offer significant productivity gains and faster performance for ASIC prototyping engineers," said Wouter Suverkropp, product line marketing manager of Virtex-6 FPGAs at Xilinx. "When used with Synopsys’ HAPS-60 series systems that can support up to 81 million ASIC gates, these releases are well suited to make the most of the Virtex-6 LX760 devices that each provide 760,000 logic cell capacity."
The latest release of the Certify also allows prototypes built with multiple HAPS boards to be brought up quickly via system target Tcl scripting as well as produce accurate static timing analysis estimates with post-route delay back annotation. It also supports encrypted DesignWare Library IP to make the transition from multiple-FPGAs to ASIC easier, and there is a new PCB trace impact analysis element.
The latest release of Identify RTL debugger increases the visibility within the FPGA prototype with debugger results annotated in the RTL View of the Synplify HDL Analyst graphical analysis tool and helps isolate defects by tracing longer periods of signal activity with up to 64 times more sample buffer capacity.
Both tools are designed for use with Synopsys’ HAPS systems, though enhancements in these latest tool releases also benefit custom and build-your-own prototypers. "As design complexity grows, it is increasingly important for developers to prototype their designs quickly and debug them efficiently," said Ed Bard, senior director of product marketing at Synopsys. "The new Identify and Certify tool releases include significant advancements in the FPGA software tool flow that directly translate to higher productivity for our HAPS users, and also ensure that designers who build their own hardware prototypes can do so faster and with less effort."
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