FPGA brings high speed SERDES to RF and communications applications
It is aimed at developing mainstream platforms for a variety of applications such as remote wireless radio heads, distributed antenna systems, cellular basestations, Ethernet aggregation, switching, routing, industrial networking, video signal processing, video and data centre system.
The ECP4 contain up to sixteen CEI-compliant 6 Gbps SERDES channels with embedded Physical Coding Sub-layer (PCS) blocks in both low cost wire-bonded and high performance flip chip packages for chip to chip as well as long haul backplane applications. The configurable SERDES/PCS can be integrated with the hardened Communication Engines to economically build complete high bandwidth sub-systems with up to 10 times the power and cost reduction of similar implementations in FPGA fabrics.
The LatticeECP4 Communication Engines portfolio includes solutions for PCI Express 2.1, multiple 10 Gigabit Ethernet MAC and Tri-speed Ethernet MACs as well as Serial Rapid I/O (SRIO) 2.1.
The DSP blocks use 18×18 multipliers, wide ALUs, adder-trees and carry chains for cascadability and a unique booster logic means each ECP4 DSP block can be equal to four of the previous generation ECP3 DSP blocks, enabling up to four times the signal processing capability of the previous generation devices. The 18×18 multipliers can be split into 9×9 or combined into 36×36 to match the application requirements and up to 576 multipliers can be cascaded together to build complex filters for wireless Remote Radio Heads (RRH), MIMO-based RF antenna solutions and video processing applications.
The devices have 1066 Mbps DDR3 memory interfaces and 1.25 Gbps LVDS I/Os that are also capable of being used as serial Gigabit Ethernet interfaces:
Customers can begin designing with LatticeECP4 FPGAs now using the Lattice Diamond 1.4 beta design software, the new flagship design environment for Lattice FPGA products. This provides a complete set of powerful tools, efficient design flows and a user interface that enables designers to more quickly target low power, cost sensitive FPGA applications. In addition, Lattice Diamond includes a very accurate power calculator, pin-based simultaneous switching output noise calculator and proven MAP and PAR FPGA implementation algorithms that help ensure low cost and low power design solutions.
Device samples will be available in the first half of 2012 and high-volume production delivery is scheduled for the second half of 2012.
For further information: www.latticesemi.com/latticediamond.
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