FPGA DDR4 interface demonstrated to run at 2400 Mbit/sec
As defined by the JEDEC JESD79-4 DDR4 DRAM specification, the Agilent N6462A DDR4 compliance test enables early adopters of DDR4 technology to make critical electrical and timing analyses for characterisation and margin-testing purposes. The DDR4 memory interface in the UltraScale All Programmable FPGAs provides more than 1 Tbit/sec of memory bandwidth to handle the massive data flow, fast processing, and enormous memory requirements of applications such as video imaging and processing, traffic management, and high-performance computing.
Agilent’s DDR4 BGA interposers allow users to gain access to the DDR4 signals that are critical to DDR4 debug and validation. The interposers work in existing designs and eliminate the need for up-front planning or re-design by providing probe points that enable designers to see the actual clock and data signals using an oscilloscope.
A video demonstration of how Agilent’s test solution validated the Xilinx UltraScale device memory solution running at 2400 Mbit/sec is at; www.xilinx.com/memory
Agilent’s DDR4 BGA Interposers; www.agilent.com/find/n6462a
Xilinx; www.xilinx.com
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