Envelope signal generation in the FPGA was implemented using Nujira’s Envelope Generation Interface, which is compliant with the openET Alliance’s specification for infrastructure ET modulators.
Xilinx says it is fully committed to supporting the cellular industry in minimising the environmental impact and operating cost of the next generation of 3G and 4G infrastructure. Envelope tracking technology is increasingly being recognised as a must-have power optimisation technology and Xilinx has therefore integrated an envelope tracking port into its 3rd generation Multimode Radio Targeted Design Platform (TDP).
According to Nujira, the integration of the openET Envelope Generation Interface with Xilinx DPD and CFR LogiCORE IP was extremely straightforward, and the design was up and running within a few hours with no major issues. The project shows that Coolteq can easily be integrated with market leading DPD solutions, and that Envelope Tracking Power Amplifiers based on Coolteq-h can be linearised using Xilinx DPD technology.
The integration was based on Nujira’s NCT-B1110 Envelope Generation Interface VHDL code integrated with Xilinx’s v4.0 Digital Predistortion LogiCORE IP block, running on a Xilinx ML605 reference platform for the Virtex 6 FPGA. A Nujira NCT-H4010 ET modulator was used with a simple FMC interface adaptor for direct connection to the ML605.
The RF path was generated by Analog Devices’ AD-MSDPD-EVB Mixed Signal Digital Pre-Distortion Evaluation Platform, and the power amplifier was a Nujira NCT-T4503 power amplifier using a SEDI EGN21B090IV GaN power transistor.
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