FPGA family targets edge computing, AI/ML and vision processing

FPGA family targets edge computing, AI/ML and vision processing

New Products |
By Julien Happich

With the integrated Cadence RTL-to-signoff flow, Efinix engineers were able to achieve first-pass success across a spectrum of nodes down to 10nm. Based on Efinix’s successful collaboration with Cadence, the company plans to continue its use of the Cadence flow to grow its Trion product line.
The Efinix Trion product family offers its customers improved power, performance and area (PPA), and therefore they required advanced power and area optimization algorithms that support a variety of nodes. The Cadence digital full flow solution addressed Efinix’s requirements and provides a unified physical optimization flow from RTL to GDSII with a common UI and database, allowing Efinix to have a seamless transition from physical synthesis to implementation. It is the industry’s only digital flow solution with fully integrated place and route, timing signoff and IR drop/power signoff technologies, enabling Efinix to achieve faster design closure with fewer iterations to speed time to market.

The Cadence digital full flow solution features the Genus Synthesis Solution, Innovus Implementation Solution, Tempus Timing Signoff Solution, Quantus Extraction Solution and Voltus IC Power Integrity Solution. The flow supports Cadence’s Intelligent System Design strategy, accelerating SoC design excellence and delivering better predictability.
Cadence Design Systems –


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