FPGA IP to embed in SoCs for function acceleration

FPGA IP to embed in SoCs for function acceleration

New Products |
By Graham Prophet

Where the intention has been (for example) to provide for late design changes, a barrier that has frequently been cited as holding back the concept is the disparity in density between FPGA structures and fully-diffused cells and blocks. Put simplistically, if you lay down enough FPGA to be useful, you use a disproportionate amount of silicon area. (The converse, embedding specific blocks of diffused IP, such as processors cores – e.g. Xilinx Zynq – has been much more successful.)


Now, Achronix (Santa Clara, California) has announced its Speedcore embedded FPGA (eFPGA) IP for integration into designer’s SoCs. Speedcore is designed for compute and network acceleration applications and is based on the same architecture that is in Achronix’s Speedster22i FPGAs that have been shipping in production since 2013.


With Speedcore, designers specify the optimal die size, power consumption and resource configuration required for their end application. They define the quantity of look-up-tables (LUTs), embedded memory blocks and DSP blocks. Additionally, designers define the Speedcore aspect ratio, IO port connections and can make tradeoffs between power and performance. Achronix delivers a GDS II of the Speedcore IP that engineeers integrate directly into their SoC, and a custom, full-featured version of the ACE design tools that customers use to design, verify and program the functionality of the Speedcore eFPGA. Speedcore eFPGA products are fully supported by Achronix’s robust and proven ACE design tools.


“Over the years, different companies have talked about eFPGA products, but Achronix Speedcore is the first eFPGA IP to ship to end customers, and it is a game changer” said Robert Blake, President and CEO, Achronix Semiconductor. “Achronix was the first company to deliver high density FPGAs with embedded system level IP. We are using that same proven methodology to deliver our eFPGA technology to customers who want to combine all the efficiencies of ASIC design with the flexibility of eFPGA programmable hardware accelerators on the same chip.”


Achronix expands its argument for eFPGA; “Compute and communications infrastructure in data centres and enterprises can no longer keep pace with exponential data growth rates, changing security and software virtualization requirements. Traditional multi-core CPUs and SoCs need programmable hardware accelerators that pre-process and offload data to increase their compute performance. FPGAs are the optimal hardware accelerator solution because accelerators need to be updated with new functionality as algorithms are constantly changing. Standalone FPGAs are a convenient and practical solution for low to medium volume applications, whereas Speedcore is the optimal solution for high volume applications and offers significant advantages


“Lower power:

– Speedcore has direct wire connections to the SoC, which eliminates the large programmable IO buffers found in standalone FPGAs. Programmable IO circuitry accounts for half of the total power consumption of standalone FPGAs.

– Speedcore is sized exactly to the requirements of the designer’s end application

– Customers can tune the process technology to tradeoff performance for lower power


“Higher interface performance:

– Speedcore offers higher interface performance than standalone FPGAs, in the form of lower latency. Speedcore is connected to the ASIC through an ultra-wide parallel interface whereas standalone FPGAs typically connect through a high-latency SerDes structure.


“Lower system cost:

– Speedcore die size is much smaller than standalone FPGAs because the programmable IO buffer structure is eliminated.

– Standalone FPGAs have high pin counts which dictate the PCB layer count to support the FPGA BGA package escape routing. Additionally, Speedcore eliminates the need for all of the support components around the FPGA including power regulators, clock generators, level shifters, passive components and FPGA cooling.


“Higher system reliability and yields:

– Integrating FPGA functionality into an ASIC improves system level signal integrity and eliminates reliability and yield loss associated with having a standalone FPGA on the PCB.”


Speedcore is architected in modular fashion to support flexibility for customers to define their resource requirements and for Achronix to rapidly configure the Speedcore IP for delivery. Additionally, the modular architecture allows Achronix to easily port the technology to different process technology nodes and metal stacks. Speedcore is now available on TSMC 16FF+ and is in development on TSMC 7nm.


Achronix’s ACE design tools include an example instance of Speedcore where customers can compile their designs today to evaluate Speedcore quality-of-results for performance, resource usage and compile times. Achronix also has complete documentation on Speedcore functionality and ASIC integration methodologies.


Achronix says it has completed several Speedcore designs in a “stealth” phase of product introduction.


Achronix Semiconductor;



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