FPGA Manager IP eases data streaming

FPGA Manager IP eases data streaming

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By Julien Happich

The solution includes a host software library, a suitable IP core for the FPGA and device controller firmware, if necessary. The user host application can communicate with the FPGA through a simple API consisting of simple read/write data commands. Streaming and memory-mapped accesses are supported. The FPGA Manager IP Solution is optimized for Altera and Xilinx FPGAs and greatly simplifies host-to-FPGA communication by hiding the complexity of the underlying protocols. It supports user applications written in C, C++, C# and MATLAB and is available for Microsoft Windows and Linux.

When data rates are especially high, PCI Express comes to the fore – FPGA Manager PCIe, with PCIe Gen1 ×4, reaches a bandwidth of over 720 MBytes/s from PC to FPGA, and almost 780 MBytes/s in the opposite direction. Enclustra is continually developing the IP cores to tweak out more performance and adapt them to new technologies — the FPGA Manager IP Solution now supports PCIe Gen2 x4, almost doubling the available bandwidth for host PC to FPGA communication.

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