FPGA/PLD chips increase I/O & control options

FPGA/PLD chips increase I/O & control options

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By eeNews Europe

Anticipating uses in control applications in server, communications, and industrial markets, Lattice positions the latest package options as offering a 60% reduction in power consumption with expanded resources for motor control and board management applications. An evaluation board offers flexibility for designing MachXO3 control PLDs into a variety of system architectures


MachXO3-9400 devices have a core voltage of 1.2V for lower power in thermally-challenged environments, provide expanded FPGA logic resources for motor control and board management functions, and offer a higher I/O count optimized for server and storage applications. The evaluation board will support a variety of system architectures, including board management, embedded microcontroller I/O expansion and video protocol bridging functions.


Device options include:

– MachXO3-9400E (1.2V core voltage) options with 60% reduced power consumption over MachXO3-9400C (3.3V core voltage) variants.

– Pin migration options from MachXO3-6900, expanding FPGA logic resources for factory automation and server board management.

– Up to 384 I/O – the highest I/O count yet in the MachXO3 family.

– MachXO3 family features such as internal configuration memory, flexible programmable I/Os and embedded memory are continued.


The MachXO3-9400 evaluation board features the MachXO3-9400 control PLD and the Lattice Hardware Management Expander, the L-ASC10. The board also includes connectors for Raspberry Pi 3, Arduino Zero, and additional expansion boards. The board is suitable for designers who are looking to quickly and efficiently implement I/O expansion, co-processing, motor control and video bridging into their latest computing and industrial applications.


Lattice; and



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